From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 12 Dec 2018 14:12:42 +0000 (-0800)
Subject: riscv: Fix context restore before returning from trap handler
X-Git-Url: http://git.dujemihanovic.xyz/img/static/gitweb.css?a=commitdiff_plain;h=496262cca63f25408c6715b39cea1747e8ce9b59;p=u-boot.git

riscv: Fix context restore before returning from trap handler

sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---

diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index a5ad558621..da307e4273 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -77,7 +77,6 @@ trap_entry:
 #endif
 	csrs MODE_PREFIX(status), t0
 	LREG x1,   1 * REGBYTES(sp)
-	LREG x2,   2 * REGBYTES(sp)
 	LREG x3,   3 * REGBYTES(sp)
 	LREG x4,   4 * REGBYTES(sp)
 	LREG x5,   5 * REGBYTES(sp)
@@ -107,5 +106,6 @@ trap_entry:
 	LREG x29, 29 * REGBYTES(sp)
 	LREG x30, 30 * REGBYTES(sp)
 	LREG x31, 31 * REGBYTES(sp)
+	LREG x2,   2 * REGBYTES(sp)
 	addi sp, sp, 32 * REGBYTES
 	MODE_PREFIX(ret)