From: Yinbo Zhu Date: Tue, 14 Apr 2020 09:24:48 +0000 (+0800) Subject: armv8: ls1028a: define esdhc_status_fixup X-Git-Url: http://git.dujemihanovic.xyz/img/static/gitweb.css?a=commitdiff_plain;h=316fc6ff762b44044ef164f51e042cb8a90dc147;p=u-boot.git armv8: ls1028a: define esdhc_status_fixup This patch is to define esdhc_status_fixup function for ls1028a to disable SDHC1/SDHC2 status in device tree node if not selected. Signed-off-by: Yinbo Zhu Signed-off-by: Xiaowei Bao Signed-off-by: Yangbo Lu Reviewed-by: Priyanka Jain --- diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 299201b157..c2fbc23b11 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -232,7 +232,12 @@ #define DCFG_PORSR1 0x000 #define DCFG_PORSR1_RCW_SRC 0xff800000 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define DCFG_RCWSR12 0x12c +#define DCFG_RCWSR12_SDHC_SHIFT 24 +#define DCFG_RCWSR12_SDHC_MASK 0x7 #define DCFG_RCWSR13 0x130 +#define DCFG_RCWSR13_SDHC_SHIFT 3 +#define DCFG_RCWSR13_SDHC_MASK 0x7 #define DCFG_RCWSR13_DSPI (0 << 8) #define DCFG_RCWSR15 0x138 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index aa93534ac6..0b7504aea1 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -135,6 +135,46 @@ void detail_board_ddr_info(void) print_ddr_info(0); } +int esdhc_status_fixup(void *blob, const char *compat) +{ + void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE; + char esdhc1_path[] = "/soc/mmc@2140000"; + char esdhc2_path[] = "/soc/mmc@2150000"; + char dspi1_path[] = "/soc/spi@2100000"; + char dspi2_path[] = "/soc/spi@2110000"; + u32 mux_sdhc1, mux_sdhc2; + u32 io = 0; + + /* + * The PMUX IO-expander for mux select is used to control + * the muxing of various onboard interfaces. + */ + + io = in_le32(dcfg_ccsr + DCFG_RCWSR12); + mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK; + + /* Disable esdhc1/dspi1 if not selected. */ + if (mux_sdhc1 != 0) + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + if (mux_sdhc1 != 2) + do_fixup_by_path(blob, dspi1_path, "status", "disabled", + sizeof("disabled"), 1); + + io = in_le32(dcfg_ccsr + DCFG_RCWSR13); + mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK; + + /* Disable esdhc2/dspi2 if not selected. */ + if (mux_sdhc2 != 0) + do_fixup_by_path(blob, esdhc2_path, "status", "disabled", + sizeof("disabled"), 1); + if (mux_sdhc2 != 2) + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); + + return 0; +} + #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) {