From: Bin Meng Date: Wed, 12 Dec 2018 14:12:43 +0000 (-0800) Subject: riscv: Return to previous privilege level after trap handling X-Git-Url: http://git.dujemihanovic.xyz/img/static/gitweb.css?a=commitdiff_plain;h=10753ef8fd14dfe1d41ec253966569de19463adc;p=u-boot.git riscv: Return to previous privilege level after trap handling At present the trap handler returns to hardcoded M-mode/S-mode. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index da307e4273..407ecfa9c0 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -68,14 +68,6 @@ trap_entry: jal handle_trap csrw MODE_PREFIX(epc), a0 -#ifdef CONFIG_RISCV_SMODE - /* Remain in S-mode after sret */ - li t0, SSTATUS_SPP -#else - /* Remain in M-mode after mret */ - li t0, MSTATUS_MPP -#endif - csrs MODE_PREFIX(status), t0 LREG x1, 1 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp)