The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.
This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
-source "arch/riscv/cpu/qemu/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
# architecture-specific options below
#
# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
-config QEMU_RISCV
+config GENERIC_RISCV
bool
select ARCH_EARLY_INIT_R
imply CPU
default "emulation"
config SYS_CPU
- default "qemu"
+ default "generic"
config SYS_CONFIG_NAME
default "qemu-riscv"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select QEMU_RISCV
+ select GENERIC_RISCV
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET