ARM: DTS: stm32: align DT clock declaration with kernel

Use the same clocks macro than the one used by kernel DT.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 54f5bc7a54e5f124ee02c135c1dc0c490e773f56..783d4e734e5873f428d6f3a992d2fde24d68a388 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -47,6 +47,8 @@
 
 #include "armv7-m.dtsi"
 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
 
 / {
        clocks {
@@ -74,7 +76,7 @@
                fmc: fmc@A0000000 {
                        compatible = "st,stm32-fmc";
                        reg = <0xA0000000 0x1000>;
-                       clocks = <&rcc 0 64>;
+                       clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
                        u-boot,dm-pre-reloc;
                };
 
@@ -86,14 +88,14 @@
                        reg-names = "QuadSPI", "QuadSPI-memory";
                        interrupts = <92>;
                        spi-max-frequency = <108000000>;
-                       clocks = <&rcc 0 65>;
+                       clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
                        status = "disabled";
                };
                usart1: serial@40011000 {
                        compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                        reg = <0x40011000 0x400>;
                        interrupts = <37>;
-                       clocks = <&rcc 0 164>;
+                       clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
                        status = "disabled";
                        u-boot,dm-pre-reloc;
                };
@@ -119,7 +121,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x0 0x400>;
-                               clocks = <&rcc 0 0>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
                                st,bank-name = "GPIOA";
                                u-boot,dm-pre-reloc;
                        };
@@ -129,7 +131,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x400 0x400>;
-                               clocks = <&rcc 0 1>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
                                st,bank-name = "GPIOB";
                                u-boot,dm-pre-reloc;
                        };
@@ -140,7 +142,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x800 0x400>;
-                               clocks = <&rcc 0 2>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
                                st,bank-name = "GPIOC";
                                u-boot,dm-pre-reloc;
                        };
@@ -150,7 +152,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0xc00 0x400>;
-                               clocks = <&rcc 0 3>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
                                st,bank-name = "GPIOD";
                                u-boot,dm-pre-reloc;
                        };
@@ -160,7 +162,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x1000 0x400>;
-                               clocks = <&rcc 0 4>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
                                st,bank-name = "GPIOE";
                                u-boot,dm-pre-reloc;
                        };
@@ -170,7 +172,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x1400 0x400>;
-                               clocks = <&rcc 0 5>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
                                st,bank-name = "GPIOF";
                                u-boot,dm-pre-reloc;
                        };
@@ -180,7 +182,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x1800 0x400>;
-                               clocks = <&rcc 0 6>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
                                st,bank-name = "GPIOG";
                                u-boot,dm-pre-reloc;
                        };
@@ -190,7 +192,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x1c00 0x400>;
-                               clocks = <&rcc 0 7>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
                                st,bank-name = "GPIOH";
                                u-boot,dm-pre-reloc;
                        };
@@ -200,7 +202,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x2000 0x400>;
-                               clocks = <&rcc 0 8>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
                                st,bank-name = "GPIOI";
                                u-boot,dm-pre-reloc;
                        };
@@ -210,7 +212,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x2400 0x400>;
-                               clocks = <&rcc 0 9>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
                                st,bank-name = "GPIOJ";
                                u-boot,dm-pre-reloc;
                        };
@@ -220,7 +222,7 @@
                                #gpio-cells = <2>;
                                compatible = "st,stm32-gpio";
                                reg = <0x2800 0x400>;
-                               clocks = <&rcc 0 10>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
                                st,bank-name = "GPIOK";
                                u-boot,dm-pre-reloc;
                        };

diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
new file mode 100644 (file)
index 0000000..49bb3c2
--- /dev/null
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -0,0 +1,59 @@
+/*
+ * stm32fx-clock.h
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ * Author: Gabriel Fernandez for STMicroelectronics.
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+/*
+ * List of clocks wich are not derived from system clock (SYSCLOCK)
+ *
+ * The index of these clocks is the secondary index of DT bindings
+ * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
+ *
+ * e.g:
+       <assigned-clocks = <&rcc 1 CLK_LSE>;
+*/
+
+#ifndef _DT_BINDINGS_CLK_STMFX_H
+#define _DT_BINDINGS_CLK_STMFX_H
+
+#define SYSTICK                        0
+#define FCLK                   1
+#define CLK_LSI                        2
+#define CLK_LSE                        3
+#define CLK_HSE_RTC            4
+#define CLK_RTC                        5
+#define PLL_VCO_I2S            6
+#define PLL_VCO_SAI            7
+#define CLK_LCD                        8
+#define CLK_I2S                        9
+#define CLK_SAI1               10
+#define CLK_SAI2               11
+#define CLK_I2SQ_PDIV          12
+#define CLK_SAIQ_PDIV          13
+
+#define END_PRIMARY_CLK                14
+
+#define CLK_HSI                        14
+#define CLK_SYSCLK             15
+#define CLK_HDMI_CEC           16
+#define CLK_SPDIF              17
+#define CLK_USART1             18
+#define CLK_USART2             19
+#define CLK_USART3             20
+#define CLK_UART4              21
+#define CLK_UART5              22
+#define CLK_USART6             23
+#define CLK_UART7              24
+#define CLK_UART8              25
+#define CLK_I2C1               26
+#define CLK_I2C2               27
+#define CLK_I2C3               28
+#define CLK_I2C4               29
+#define CLK_LPTIMER            30
+
+#define END_PRIMARY_CLK_F7     31
+
+#endif

diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
new file mode 100644 (file)
index 0000000..e36cc69
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -0,0 +1,112 @@
+/*
+ * This header provides constants for the STM32F7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
+#define _DT_BINDINGS_MFD_STM32F7_RCC_H
+
+/* AHB1 */
+#define STM32F7_RCC_AHB1_GPIOA         0
+#define STM32F7_RCC_AHB1_GPIOB         1
+#define STM32F7_RCC_AHB1_GPIOC         2
+#define STM32F7_RCC_AHB1_GPIOD         3
+#define STM32F7_RCC_AHB1_GPIOE         4
+#define STM32F7_RCC_AHB1_GPIOF         5
+#define STM32F7_RCC_AHB1_GPIOG         6
+#define STM32F7_RCC_AHB1_GPIOH         7
+#define STM32F7_RCC_AHB1_GPIOI         8
+#define STM32F7_RCC_AHB1_GPIOJ         9
+#define STM32F7_RCC_AHB1_GPIOK         10
+#define STM32F7_RCC_AHB1_CRC           12
+#define STM32F7_RCC_AHB1_BKPSRAM       18
+#define STM32F7_RCC_AHB1_DTCMRAM       20
+#define STM32F7_RCC_AHB1_DMA1          21
+#define STM32F7_RCC_AHB1_DMA2          22
+#define STM32F7_RCC_AHB1_DMA2D         23
+#define STM32F7_RCC_AHB1_ETHMAC                25
+#define STM32F7_RCC_AHB1_ETHMACTX      26
+#define STM32F7_RCC_AHB1_ETHMACRX      27
+#define STM32FF_RCC_AHB1_ETHMACPTP     28
+#define STM32F7_RCC_AHB1_OTGHS         29
+#define STM32F7_RCC_AHB1_OTGHSULPI     30
+
+#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
+
+
+/* AHB2 */
+#define STM32F7_RCC_AHB2_DCMI          0
+#define STM32F7_RCC_AHB2_CRYP          4
+#define STM32F7_RCC_AHB2_HASH          5
+#define STM32F7_RCC_AHB2_RNG           6
+#define STM32F7_RCC_AHB2_OTGFS         7
+
+#define STM32F7_AHB2_RESET(bit)        (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F7_AHB2_CLOCK(bit)        (STM32F7_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F7_RCC_AHB3_FMC           0
+#define STM32F7_RCC_AHB3_QSPI          1
+
+#define STM32F7_AHB3_RESET(bit)        (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F7_AHB3_CLOCK(bit)        (STM32F7_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F7_RCC_APB1_TIM2          0
+#define STM32F7_RCC_APB1_TIM3          1
+#define STM32F7_RCC_APB1_TIM4          2
+#define STM32F7_RCC_APB1_TIM5          3
+#define STM32F7_RCC_APB1_TIM6          4
+#define STM32F7_RCC_APB1_TIM7          5
+#define STM32F7_RCC_APB1_TIM12         6
+#define STM32F7_RCC_APB1_TIM13         7
+#define STM32F7_RCC_APB1_TIM14         8
+#define STM32F7_RCC_APB1_LPTIM1                9
+#define STM32F7_RCC_APB1_WWDG          11
+#define STM32F7_RCC_APB1_SPI2          14
+#define STM32F7_RCC_APB1_SPI3          15
+#define STM32F7_RCC_APB1_SPDIFRX       16
+#define STM32F7_RCC_APB1_UART2         17
+#define STM32F7_RCC_APB1_UART3         18
+#define STM32F7_RCC_APB1_UART4         19
+#define STM32F7_RCC_APB1_UART5         20
+#define STM32F7_RCC_APB1_I2C1          21
+#define STM32F7_RCC_APB1_I2C2          22
+#define STM32F7_RCC_APB1_I2C3          23
+#define STM32F7_RCC_APB1_I2C4          24
+#define STM32F7_RCC_APB1_CAN1          25
+#define STM32F7_RCC_APB1_CAN2          26
+#define STM32F7_RCC_APB1_CEC           27
+#define STM32F7_RCC_APB1_PWR           28
+#define STM32F7_RCC_APB1_DAC           29
+#define STM32F7_RCC_APB1_UART7         30
+#define STM32F7_RCC_APB1_UART8         31
+
+#define STM32F7_APB1_RESET(bit)        (STM32F7_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F7_APB1_CLOCK(bit)        (STM32F7_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F7_RCC_APB2_TIM1          0
+#define STM32F7_RCC_APB2_TIM8          1
+#define STM32F7_RCC_APB2_USART1                4
+#define STM32F7_RCC_APB2_USART6                5
+#define STM32F7_RCC_APB2_ADC1          8
+#define STM32F7_RCC_APB2_ADC2          9
+#define STM32F7_RCC_APB2_ADC3          10
+#define STM32F7_RCC_APB2_SDMMC1                11
+#define STM32F7_RCC_APB2_SPI1          12
+#define STM32F7_RCC_APB2_SPI4          13
+#define STM32F7_RCC_APB2_SYSCFG                14
+#define STM32F7_RCC_APB2_TIM9          16
+#define STM32F7_RCC_APB2_TIM10         17
+#define STM32F7_RCC_APB2_TIM11         18
+#define STM32F7_RCC_APB2_SPI5          20
+#define STM32F7_RCC_APB2_SPI6          21
+#define STM32F7_RCC_APB2_SAI1          22
+#define STM32F7_RCC_APB2_SAI2          23
+#define STM32F7_RCC_APB2_LTDC          26
+
+#define STM32F7_APB2_RESET(bit)        (STM32F7_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F7_APB2_CLOCK(bit)        (STM32F7_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */