sunxi: clock: H6/H616: Fix PLL clock factor encodings

Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.

This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000

Also the CPU frequency (PLL1) was a tad too high before.

For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 62abfc4ef6bd59401dfc66b2df05173816b6a9c0..2e076cf594daffba89149cf8a82888849cc74fd4 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -233,14 +233,14 @@ struct sunxi_ccm_reg {
 #define CCM_PLL1_OUT_EN                        BIT(27)
 #define CCM_PLL1_CLOCK_TIME_2          (2 << 24)
 #define CCM_PLL1_CTRL_P(p)             ((p) << 16)
-#define CCM_PLL1_CTRL_N(n)             ((n) << 8)
+#define CCM_PLL1_CTRL_N(n)             (((n) - 1) << 8)
 
 /* pll5 bit field */
 #define CCM_PLL5_CTRL_EN               BIT(31)
 #define CCM_PLL5_LOCK_EN               BIT(29)
 #define CCM_PLL5_LOCK                  BIT(28)
 #define CCM_PLL5_OUT_EN                        BIT(27)
-#define CCM_PLL5_CTRL_N(n)             ((n) << 8)
+#define CCM_PLL5_CTRL_N(n)             (((n) - 1) << 8)
 #define CCM_PLL5_CTRL_DIV1(div1)       ((div1) << 0)
 #define CCM_PLL5_CTRL_DIV2(div0)       ((div0) << 1)
 

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 492fc4a3fca8ab8c018634149991bda052444336..a947463e0a53d883733c3fbd7352ae2e456c5812 100644 (file)
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void)
        int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
 
        uint32_t rval = readl(&ccm->pll6_cfg);
-       int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+       int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
        int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
                        CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
        int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 32ec0bc4cd4ffd49607ac8ad03da2489d863084d..d05375c902772d254d8749948c1a3f38ebe5b6d7 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -171,7 +171,7 @@ static void mctl_sys_init(struct dram_para *para)
 
        /* Set PLL5 rate to doubled DRAM clock rate */
        writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
-              CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
+              CCM_PLL5_CTRL_N(para->clk * 2 / 24), &ccm->pll5_cfg);
        mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
 
        /* Configure DRAM mod clock */

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index ef5876971ca1ba77a2c9994e314f5adffaa62a5f..acdfb3ceef8ca06e6130a4c3763f1c857d87d598 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -113,7 +113,7 @@ static void mctl_sys_init(struct dram_para *para)
 
        /* Set PLL5 rate to doubled DRAM clock rate */
        writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN |
-              CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
+              CCM_PLL5_CTRL_N(para->clk * 2 / 24), &ccm->pll5_cfg);
        mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
 
        /* Configure DRAM mod clock */