powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL

e500v2 processor does not support 8K page size TLB entries.

So create new TLB entry only during NAND SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index 8a7c0ecb029c97f12b7e01412efd85c41a67bb5d..c05a556a3dcc69ba36ebbdfea96ed95e02c6f943 100644 (file)
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
        /* TLB 1 */
        /* *I*** - Covers boot page */
-               SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
-                             MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                             0, 0, BOOKE_PAGESZ_8K, 1),
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+       SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
        /* *I*G* - CCSRBAR (PA) */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,

diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 9263a470618804863d5549903be83999c0325a1a..0ec9a851aba6ad55a0ad5b5ce68ab9a20759a602 100644 (file)
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
        /* TLB 1 */
        /* *I*** - Covers boot page */
-               SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
-                             MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                             0, 0, BOOKE_PAGESZ_8K, 1),
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+       SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
        /* *I*G* - CCSRBAR (PA) */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,

diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 7a8690a90d90dacb3128fdc256057807bc157dd5..0a8159a6a510f810795012cea040ef8c0b01e2fd 100644 (file)
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
        /* TLB 1 */
        /* *I*** - Covers boot page */
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
        SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 0, BOOKE_PAGESZ_8K, 1),
+                     0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
        /* *I*G* - CCSRBAR */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,