net: zynq: Add clk framework support to zynq ethernet driver

If available use the clock framework to set the tx clock rate of the
zynq ethernet controller.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 8c54fcedf40108fcc297e825c21e3ef3fbd28d80..7b11895481be584d8f3af904d0bf9cefe2a51fb9 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -8,13 +8,6 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
-#ifndef CONFIG_CLK_ZYNQMP
-/* Setup clk for network */
-static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
-{
-}
-#endif
-
 int zynq_slcr_get_mio_pin_status(const char *periph);
 
 unsigned int zynqmp_get_silicon_version(void);

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index d3c33e801d62862ea9608815f08d3c796b91a28e..36397fe053835c42d87974b6b1fc94a7bb4d5716 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -181,7 +181,7 @@ struct zynq_gem_priv {
        struct phy_device *phydev;
        int phy_of_handle;
        struct mii_dev *bus;
-#ifdef CONFIG_CLK_ZYNQMP
+#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
        struct clk clk;
 #endif
 };
@@ -456,13 +456,21 @@ static int zynq_gem_init(struct udevice *dev)
                break;
        }
 
-#ifndef CONFIG_CLK_ZYNQMP
+#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
+       ret = clk_set_rate(&priv->clk, clk_rate);
+       if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+               dev_err(dev, "failed to set tx clock rate\n");
+               return ret;
+       }
+
+       ret = clk_enable(&priv->clk);
+       if (ret && ret != -ENOSYS) {
+               dev_err(dev, "failed to enable tx clock\n");
+               return ret;
+       }
+#else
        zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
                                ZYNQ_GEM_BASEADDR0, clk_rate);
-#else
-       ret = clk_set_rate(&priv->clk, clk_rate);
-       if (IS_ERR_VALUE(ret))
-               return -1;
 #endif
 
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
@@ -636,7 +644,7 @@ static int zynq_gem_probe(struct udevice *dev)
        priv->tx_bd = (struct emac_bd *)bd_space;
        priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 
-#ifdef CONFIG_CLK_ZYNQMP
+#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
        ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
        if (ret < 0) {
                dev_err(dev, "failed to get clock\n");