mtd: spi-nor-core: Consider reserved bits in CFR5 register

CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition,
stop using magic numbers and describe the missing bit fields in CFR5
register. This is useful for both readability and future possible addition
of Octal STR mode support.

Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash")
Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 30f15452aa687b142e82309479666bfab6e5b4e6..2fb4595fc756d30913232b31fc087b6ac5b5cd07 100644 (file)
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -194,7 +194,12 @@
 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ          BIT(4) /* Page size. */
 #define SPINOR_REG_CYPRESS_CFR3V_UNISECT       BIT(3) /* Uniform sector mode */
 #define SPINOR_REG_CYPRESS_CFR5V               0x00800006
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN    0x3
+#define SPINOR_REG_CYPRESS_CFR5_BIT6           BIT(6)
+#define SPINOR_REG_CYPRESS_CFR5_DDR            BIT(1)
+#define SPINOR_REG_CYPRESS_CFR5_OPI            BIT(0)
+#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN                            \
+       (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR |   \
+        SPINOR_REG_CYPRESS_CFR5_OPI)
 #define SPINOR_OP_CYPRESS_RD_FAST              0xee
 
 /* Supported SPI protocols */