]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
configs: Migrate CORTINA_FW_ADDR and CORTINA_FW_LENGTH to Kconfig
authorKuldeep Singh <kuldeep.singh@nxp.com>
Tue, 10 Aug 2021 05:50:07 +0000 (11:20 +0530)
committerPriyanka Jain <priyanka.jain@nxp.com>
Wed, 18 Aug 2021 10:25:15 +0000 (15:55 +0530)
Use moveconfig.py script to convert below defines to Kconfig and move
these entries to defconfigs.
    CONFIG_CORTINA_FW_ADDR
    CONFIG_CORTINA_FW_LENGTH

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
21 files changed:
configs/T2080RDB_NAND_defconfig
configs/T2080RDB_SDCARD_defconfig
configs/T2080RDB_SPIFLASH_defconfig
configs/T2080RDB_defconfig
configs/T2080RDB_revD_NAND_defconfig
configs/T2080RDB_revD_SDCARD_defconfig
configs/T2080RDB_revD_SPIFLASH_defconfig
configs/T2080RDB_revD_defconfig
configs/T4240RDB_SDCARD_defconfig
configs/T4240RDB_defconfig
configs/ls2080ardb_SECURE_BOOT_defconfig
configs/ls2080ardb_defconfig
configs/ls2080ardb_nand_defconfig
configs/ls2081ardb_defconfig
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
configs/ls2088ardb_qspi_defconfig
drivers/net/phy/Kconfig
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/ls2080ardb.h
scripts/config_whitelist.txt

index 95a2c778fc00a490455eb7a4e1d145a2ddbf93c4..93d8d4ba56e488d4a6367ba40c9554e2587cd186 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_NAND=y
+CONFIG_CORTINA_FW_ADDR=0x200000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 21d22df4eb3e436582ad7d2c5f5663c53537bf09..10598804a1fe9caa5cd93a56cd192895c5eb6855 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_MMC=y
+CONFIG_CORTINA_FW_ADDR=0x114000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 393b6db286328ce68a41305d14487de10243ceab..59963fdf3741ce3a73999012bf8c182c48b3767d 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
+CONFIG_CORTINA_FW_ADDR=0x120000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 24e927c735076a23cccd426072669c9fd64e146f..466e91743f50f78fb8b1949affbc64261008c6e1 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0xEFE00000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 250c2d5e962a4a8b3c9a07048037aea062e61694..f6eeade2a39dce1442fee006779f90870f3094fe 100644 (file)
@@ -70,6 +70,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_NAND=y
+CONFIG_CORTINA_FW_ADDR=0x200000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index d5eea40797abbf35618b3976b6d0accd2c3540ba..0286610cb03bedd05960d52b75e3fbbdb82fd1a1 100644 (file)
@@ -67,6 +67,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_MMC=y
+CONFIG_CORTINA_FW_ADDR=0x114000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 4d38f4b978f8bbed97971e8360ed9a525fb4c82e..eb073ce4be5f0da6b61035a3638e1173c397ae93 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
+CONFIG_CORTINA_FW_ADDR=0x120000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 2ecbabf99ec44615c158c505a4273881bfae57b7..ab7096e520255418b66cb35496b511f3979284da 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0xEFE00000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 2230e674fcb2503ce979b730bd1523623c71a8aa..c1ca2565e2697da27d2a01bd9d629d5ab8247d1a 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0x77f000
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
 CONFIG_DM_ETH=y
index abb2137d91ee06078024f96d513cc6dba05d094d..14594b0579108609004352e077e67bfec452dfca 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0xefe00000
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
 CONFIG_DM_ETH=y
index b1477eac141614fb6cf83a1459ff80629a26a74a..365ee87bdbc55413936cc3c1d780bbfbf0e6ac8a 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0x580980000
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME=y
index c107bcddad766ab74a05086566de2b8f96b104a9..cb46f4e4bbcd3fdbff64f7114fa6e73a4e5a70bf 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0x580980000
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME=y
index 6615958ae4ea1438bc9813b3ebab4383c7a53394..d371fa5e69b2d87d5451ea98db72b5501ac04be5 100644 (file)
@@ -58,6 +58,7 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0x980000
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME=y
index da02de270fb52ded5c5080c7ffbc0fd3bed36e68..26692b2e73e78b7008d5cb53a17b231e9523cd32 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0x980000
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME=y
index 0201fce1a72008bd16734c2edeaf77d03cd21ca4..bd16602413f9aa40aaa260db9852e76bf4e2e601 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0x980000
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 336a0a7b32be55c1f87df478cb0b72beff00990b..3a426031b91868c043016386d1c8715bf359c7c4 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_CORTINA_FW_ADDR=0x980000
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 405bf7675308c4a3e0ff1ec010f030ad9e566271..64d5ddf238507b9c49c2b8ccdd40330dde80fd5b 100644 (file)
@@ -131,6 +131,16 @@ config SYS_CORTINA_FW_IN_SPIFLASH
 
 endchoice
 
+config CORTINA_FW_ADDR
+       hex "Cortina Firmware Address"
+       depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
+       default 0x0
+
+config CORTINA_FW_LENGTH
+       hex "Cortina Firmware Length"
+       depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
+       default 0x40000
+
 config PHY_CORTINA_ACCESS
        bool "Cortina Access Ethernet PHYs support"
        default y
index 63cc5af2c6da789600111b61fc68d82084aff196..601e67c80c308434d5405ac3970a9247f16270c4 100644 (file)
@@ -479,7 +479,6 @@ unsigned long get_board_ddr_clk(void);
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_FMAN_FW_ADDR                0x110000
-#define CONFIG_CORTINA_FW_ADDR         0x120000
 
 #elif defined(CONFIG_SDCARD)
 /*
@@ -488,11 +487,9 @@ unsigned long get_board_ddr_clk(void);
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_FMAN_FW_ADDR                (512 * 0x820)
-#define CONFIG_CORTINA_FW_ADDR         (512 * 0x8a0)
 
 #elif defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_FMAN_FW_ADDR                (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_CORTINA_FW_ADDR         (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
@@ -502,17 +499,14 @@ unsigned long get_board_ddr_clk(void);
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_FMAN_FW_ADDR                0xFFE00000
-#define CONFIG_CORTINA_FW_ADDR         0xFFE10000
 #else
 #define CONFIG_SYS_FMAN_FW_ADDR                0xEFF00000
-#define CONFIG_CORTINA_FW_ADDR         0xEFE00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
 #define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_CORTINA_FW_LENGTH       0x40000
 #define RGMII_PHY1_ADDR                0x01  /* RealTek RTL8211E */
 #define RGMII_PHY2_ADDR                0x02
 #define CORTINA_PHY_ADDR1      0x0c  /* Cortina CS4315 */
index 57a39fa970f575025e1ba80df59ca9bc5f2ac695..c796b1d7ed0552703dbe60dd3ccfaa472d4060b9 100644 (file)
@@ -517,8 +517,6 @@ unsigned long get_board_ddr_clk(void);
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_CORTINA_FW_ADDR         0xefe00000
-#define CONFIG_CORTINA_FW_LENGTH       0x40000
 #define SGMII_PHY_ADDR1 0x0
 #define SGMII_PHY_ADDR2 0x1
 #define SGMII_PHY_ADDR3 0x2
index 49c2cc573bcd3cc4624b012012cc6365678baacb..bfbde1da9785eb72b8c72997efffbe1ddb17b995 100644 (file)
@@ -560,14 +560,6 @@ unsigned long get_board_sys_clk(void);
 #endif
 
 /* MAC/PHY configuration */
-#ifdef CONFIG_FSL_MC_ENET
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_CORTINA_FW_ADDR         0x20980000
-#else
-#define CONFIG_CORTINA_FW_ADDR         0x580980000
-#endif
-#define CONFIG_CORTINA_FW_LENGTH       0x40000
-
 #define CORTINA_PHY_ADDR1      0x10
 #define CORTINA_PHY_ADDR2      0x11
 #define CORTINA_PHY_ADDR3      0x12
@@ -577,9 +569,7 @@ unsigned long get_board_sys_clk(void);
 #define AQ_PHY_ADDR3           0x02
 #define AQ_PHY_ADDR4           0x03
 #define AQR405_IRQ_MASK                0x36
-
 #define CONFIG_ETHPRIME                "DPMAC1@xgmii"
-#endif
 
 #include <asm/fsl_secure_boot.h>
 
index 2d70bf5da7c5e3a89ab88f1cf690c1aacd867b07..d86f35856f788b5a63be513f72cee7f0f6c1490e 100644 (file)
@@ -190,8 +190,6 @@ CONFIG_CONS_SCIF1
 CONFIG_CONS_SCIF2
 CONFIG_CONS_SCIF4
 CONFIG_CON_ROT
-CONFIG_CORTINA_FW_ADDR
-CONFIG_CORTINA_FW_LENGTH
 CONFIG_CPLD_BR_PRELIM
 CONFIG_CPLD_OR_PRELIM
 CONFIG_CPM2