clock-output-names = "gemtraceclk";
};
- chipstmxptclk: chipstmxptclk {
+ chipstmxptclk: chipstmxptclk@2310164 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-divider-clock";
clocks = <&mainmuxclk>;
clock-output-names = "chipclk1rstiso112";
};
- clkmodrst0: clkmodrst0 {
+ clkmodrst0: clkmodrst0@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk16>;
};
- clkusb: clkusb {
+ clkusb: clkusb@2350008 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk16>;
domain-id = <0>;
};
- clkaemifspi: clkaemifspi {
+ clkaemifspi: clkaemifspi@235000c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk16>;
};
- clkdebugsstrc: clkdebugsstrc {
+ clkdebugsstrc: clkdebugsstrc@2350014 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <1>;
};
- clktetbtrc: clktetbtrc {
+ clktetbtrc: clktetbtrc@2350018 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <1>;
};
- clkpa: clkpa {
+ clkpa: clkpa@235001c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&paclk13>;
domain-id = <2>;
};
- clkcpgmac: clkcpgmac {
+ clkcpgmac: clkcpgmac@2350020 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkpa>;
domain-id = <2>;
};
- clksa: clksa {
+ clksa: clksa@2350024 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkpa>;
domain-id = <2>;
};
- clkpcie: clkpcie {
+ clkpcie: clkpcie@2350028 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <3>;
};
- clksr: clksr {
+ clksr: clksr@2350034 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1rstiso112>;
domain-id = <6>;
};
- clkgem0: clkgem0 {
+ clkgem0: clkgem0@235003c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <8>;
};
- clkddr30: clkddr30 {
+ clkddr30: clkddr30@235005c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <16>;
};
- clkwdtimer0: clkwdtimer0 {
+ clkwdtimer0: clkwdtimer0@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkwdtimer1: clkwdtimer1 {
+ clkwdtimer1: clkwdtimer1@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkwdtimer2: clkwdtimer2 {
+ clkwdtimer2: clkwdtimer2@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkwdtimer3: clkwdtimer3 {
+ clkwdtimer3: clkwdtimer3@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clktimer15: clktimer15 {
+ clktimer15: clktimer15@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkuart0: clkuart0 {
+ clkuart0: clkuart0@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkuart1: clkuart1 {
+ clkuart1: clkuart1@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkaemif: clkaemif {
+ clkaemif: clkaemif@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkaemifspi>;
domain-id = <0>;
};
- clkusim: clkusim {
+ clkusim: clkusim@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clki2c: clki2c {
+ clki2c: clki2c@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkspi: clkspi {
+ clkspi: clkspi@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkaemifspi>;
domain-id = <0>;
};
- clkgpio: clkgpio {
+ clkgpio: clkgpio@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkkeymgr: clkkeymgr {
+ clkkeymgr: clkkeymgr@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
reg-names = "control";
};
- clkusb1: clkusb1 {
+ clkusb1: clkusb1@2350004 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk16>;
domain-id = <0>;
};
- clkhyperlink0: clkhyperlink0 {
+ clkhyperlink0: clkhyperlink0@2350030 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <5>;
};
- clkpcie1: clkpcie1 {
+ clkpcie1: clkpcie1@235006c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <18>;
};
- clkxge: clkxge {
+ clkxge: clkxge@23500c8 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
#include "keystone-k2e.dtsi"
/ {
- compatible = "ti,k2e-evm","ti,keystone";
+ compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
model = "Texas Instruments Keystone 2 Edison EVM";
soc {
&spi0 {
status = "okay";
- nor_flash: n25q128a11@0 {
+ nor_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "Micron,n25q128a11", "jedec,spi-nor";
#size-cells = <1>;
clocks = <&chipclk13>;
ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0 0x10000>;
+ queue-range = <0 0x2000>;
+ linkram0 = <0x100000 0x4000>;
+ linkram1 = <0 0x10000>;
qmgrs {
#address-cells = <1>;
interfaces {
gbe0: interface-0 {
slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
+ link-interface = <1>;
+ phy-handle = <ðphy0>;
};
gbe1: interface-1 {
slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
+ link-interface = <1>;
+ phy-handle = <ðphy1>;
};
};
secondary-slave-ports {
port-2 {
slave-port = <2>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-3 {
slave-port = <3>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-4 {
slave-port = <4>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-5 {
slave-port = <5>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-6 {
slave-port = <6>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-7 {
slave-port = <7>;
- link-interface = <2>;
+ link-interface = <2>;
};
};
};
usb: usb@2680000 {
interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- dwc3@2690000 {
+ usb@2690000 {
interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
};
};
dma-ranges;
status = "disabled";
- dwc3@25010000 {
+ usb@25010000 {
compatible = "synopsys,dwc3";
reg = <0x25010000 0x70000>;
interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
clock-names = "pcie";
#address-cells = <3>;
#size-cells = <2>;
- reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+ reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
};
mdio: mdio@24200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x24200f00 0x100>;
status = "disabled";
clocks = <&clkcpgmac>;
clock-names = "fck";
- bus_freq = <2500000>;
+ bus_freq = <2500000>;
};
/include/ "keystone-k2e-netcp.dtsi"
};
&qspi {
status = "okay";
- flash0: m25p80@0 {
- compatible = "s25fl512s","jedec,spi-nor";
+ flash0: flash@0 {
+ compatible = "s25fl512s", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
&qspi {
status = "okay";
- flash0: m25p80@0 {
+ flash0: flash@0 {
compatible = "s25fl256s1", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
/* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
clock-names = "nss_vclk";
ranges;
- queue-range = <0 0x80>;
- linkram0 = <0x4020000 0x7ff>;
+ queue-range = <0 0x80>;
+ linkram0 = <0x4020000 0x7ff>;
qmgrs {
#address-cells = <1>;
dma_gbe: dma_gbe@0 {
reg = <0x4010000 0x100>,
- <0x4011000 0x2a0>, /* 21 Tx channels */
- <0x4012000 0x400>, /* 32 Rx channels */
- <0x4010100 0x80>,
- <0x4013000 0x400>; /* 32 Rx flows */
+ <0x4011000 0x2a0>, /* 21 Tx channels */
+ <0x4012000 0x400>, /* 32 Rx channels */
+ <0x4010100 0x80>,
+ <0x4013000 0x400>; /* 32 Rx flows */
reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
+ "txsched", "rxflow";
};
};
reg = <0x2620110 0x8>;
reg-names = "efuse";
compatible = "ti,netcp-1.0";
- status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
+ status = "disabled";
/* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
/* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
clock-names = "ethss_clk";
interfaces {
gbe0: interface-0 {
slave-port = <0>;
- link-interface = <5>;
+ link-interface = <5>;
};
};
};
};
};
- gic: interrupt-controller {
+ gic: interrupt-controller@2561000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg-names = "control";
};
- clktsip: clktsip {
+ clktsip: clktsip@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk16>;
domain-id = <0>;
};
- clksrio: clksrio {
+ clksrio: clksrio@235002c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1rstiso13>;
domain-id = <4>;
};
- clkhyperlink0: clkhyperlink0 {
+ clkhyperlink0: clkhyperlink0@2350030 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <5>;
};
- clkgem1: clkgem1 {
+ clkgem1: clkgem1@2350040 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <9>;
};
- clkgem2: clkgem2 {
+ clkgem2: clkgem2@2350044 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <10>;
};
- clkgem3: clkgem3 {
+ clkgem3: clkgem3@2350048 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <11>;
};
- clkgem4: clkgem4 {
+ clkgem4: clkgem4@235004c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <12>;
};
- clkgem5: clkgem5 {
+ clkgem5: clkgem5@2350050 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <13>;
};
- clkgem6: clkgem6 {
+ clkgem6: clkgem6@2350054 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <14>;
};
- clkgem7: clkgem7 {
+ clkgem7: clkgem7@2350058 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <15>;
};
- clkddr31: clkddr31 {
+ clkddr31: clkddr31@2350060 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <16>;
};
- clktac: clktac {
+ clktac: clktac@2350064 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <17>;
};
- clkrac01: clkrac01 {
+ clkrac01: clkrac01@2350068 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <17>;
};
- clkrac23: clkrac23 {
+ clkrac23: clkrac23@235006c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <18>;
};
- clkfftc0: clkfftc0 {
+ clkfftc0: clkfftc0@2350070 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <19>;
};
- clkfftc1: clkfftc1 {
+ clkfftc1: clkfftc1@2350074 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <19>;
};
- clkfftc2: clkfftc2 {
+ clkfftc2: clkfftc2@2350078 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <20>;
};
- clkfftc3: clkfftc3 {
+ clkfftc3: clkfftc3@235007c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <20>;
};
- clkfftc4: clkfftc4 {
+ clkfftc4: clkfftc4@2350080 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <20>;
};
- clkfftc5: clkfftc5 {
+ clkfftc5: clkfftc5@2350084 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <20>;
};
- clkaif: clkaif {
+ clkaif: clkaif@2350088 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <21>;
};
- clktcp3d0: clktcp3d0 {
+ clktcp3d0: clktcp3d0@235008c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <22>;
};
- clktcp3d1: clktcp3d1 {
+ clktcp3d1: clktcp3d1@2350090 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <22>;
};
- clktcp3d2: clktcp3d2 {
+ clktcp3d2: clktcp3d2@2350094 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <23>;
};
- clktcp3d3: clktcp3d3 {
+ clktcp3d3: clktcp3d3@2350098 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <23>;
};
- clkvcp0: clkvcp0 {
+ clkvcp0: clkvcp0@235009c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkvcp1: clkvcp1 {
+ clkvcp1: clkvcp1@23500a0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkvcp2: clkvcp2 {
+ clkvcp2: clkvcp2@23500a4 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkvcp3: clkvcp3 {
+ clkvcp3: clkvcp3@23500a8 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkvcp4: clkvcp4 {
+ clkvcp4: clkvcp4@23500ac {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <25>;
};
- clkvcp5: clkvcp5 {
+ clkvcp5: clkvcp5@23500b0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <25>;
};
- clkvcp6: clkvcp6 {
+ clkvcp6: clkvcp6@23500b4 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <25>;
};
- clkvcp7: clkvcp7 {
+ clkvcp7: clkvcp7@23500b8 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <25>;
};
- clkbcp: clkbcp {
+ clkbcp: clkbcp@23500bc {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <26>;
};
- clkdxb: clkdxb {
+ clkdxb: clkdxb@23500c0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <27>;
};
- clkhyperlink1: clkhyperlink1 {
+ clkhyperlink1: clkhyperlink1@23500c4 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <28>;
};
- clkxge: clkxge {
+ clkxge: clkxge@23500c8 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
leds {
compatible = "gpio-leds";
- debug1_1 {
+ led-debug-1-1 {
label = "keystone:green:debug1";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
};
- debug1_2 {
+ led-debug-1-2 {
label = "keystone:red:debug1";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
};
- debug2 {
+ led-debug-2 {
label = "keystone:blue:debug2";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
};
- debug3 {
+ led-debug-3 {
label = "keystone:blue:debug3";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
};
&spi0 {
status = "okay";
- nor_flash: n25q128a11@0 {
+ nor_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "Micron,n25q128a11", "jedec,spi-nor";
#size-cells = <1>;
clocks = <&chipclk13>;
ranges;
- queue-range = <0 0x4000>;
- linkram0 = <0x100000 0x8000>;
- linkram1 = <0x0 0x10000>;
+ queue-range = <0 0x4000>;
+ linkram0 = <0x100000 0x8000>;
+ linkram1 = <0x0 0x10000>;
qmgrs {
#address-cells = <1>;
"region", "push", "pop";
};
};
+
queue-pools {
qpend {
qpend-0 {
};
};
};
+
descriptor-regions {
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
/* NetCP address range */
- ranges = <0 0x2000000 0x100000>;
+ ranges = <0 0x2000000 0x100000>;
clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
dma-coherent;
secondary-slave-ports {
port-2 {
slave-port = <2>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-3 {
slave-port = <3>;
- link-interface = <2>;
+ link-interface = <2>;
};
};
};
reg-names = "control";
};
- clkdfeiqnsys: clkdfeiqnsys {
+ clkdfeiqnsys: clkdfeiqnsys@2350004 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <0>;
};
- clkpcie1: clkpcie1 {
+ clkpcie1: clkpcie1@235002c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
domain-id = <4>;
};
- clkgem1: clkgem1 {
+ clkgem1: clkgem1@2350040 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <9>;
};
- clkgem2: clkgem2 {
+ clkgem2: clkgem2@2350044 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <10>;
};
- clkgem3: clkgem3 {
+ clkgem3: clkgem3@2350048 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
domain-id = <11>;
};
- clktac: clktac {
+ clktac: clktac@2350064 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <17>;
};
- clkrac: clkrac {
+ clkrac: clkrac@2350068 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <17>;
};
- clkdfepd0: clkdfepd0 {
+ clkdfepd0: clkdfepd0@235006c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <18>;
};
- clkfftc0: clkfftc0 {
+ clkfftc0: clkfftc0@2350070 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <19>;
};
- clkosr: clkosr {
+ clkosr: clkosr@2350088 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <21>;
};
- clktcp3d0: clktcp3d0 {
+ clktcp3d0: clktcp3d0@235008c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <22>;
};
- clktcp3d1: clktcp3d1 {
+ clktcp3d1: clktcp3d1@2350094 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <23>;
};
- clkvcp0: clkvcp0 {
+ clkvcp0: clkvcp0@235009c {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkvcp1: clkvcp1 {
+ clkvcp1: clkvcp1@23500a0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkvcp2: clkvcp2 {
+ clkvcp2: clkvcp2@23500a4 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkvcp3: clkvcp3 {
+ clkvcp3: clkvcp3@23500a8 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <24>;
};
- clkbcp: clkbcp {
+ clkbcp: clkbcp@23500bc {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <26>;
};
- clkdfepd1: clkdfepd1 {
+ clkdfepd1: clkdfepd1@23500c0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <27>;
};
- clkfftc1: clkfftc1 {
+ clkfftc1: clkfftc1@23500c4 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <28>;
};
- clkiqnail: clkiqnail {
+ clkiqnail: clkiqnail@23500c8 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
domain-id = <29>;
};
- clkuart2: clkuart2 {
+ clkuart2: clkuart2@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
domain-id = <0>;
};
- clkuart3: clkuart3 {
+ clkuart3: clkuart3@2350000 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
&spi0 {
status ="okay";
- nor_flash: n25q128a11@0 {
+ nor_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "Micron,n25q128a11", "jedec,spi-nor";
#size-cells = <1>;
clocks = <&chipclk13>;
ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
+ queue-range = <0 0x2000>;
+ linkram0 = <0x100000 0x4000>;
+ linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
qmgrs {
#address-cells = <1>;
};
};
};
+
descriptor-regions {
#address-cells = <1>;
#size-cells = <1>;
interfaces {
gbe0: interface-0 {
slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
+ link-interface = <1>;
+ phy-handle = <ðphy0>;
};
gbe1: interface-1 {
slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
+ link-interface = <1>;
+ phy-handle = <ðphy1>;
};
};
secondary-slave-ports {
port-2 {
slave-port = <2>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-3 {
slave-port = <3>;
- link-interface = <2>;
+ link-interface = <2>;
};
};
};
soc {
/include/ "keystone-k2l-clocks.dtsi"
- uart2: serial@02348400 {
+ uart2: serial@2348400 {
compatible = "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02348400 0x100>;
- clocks = <&clkuart2>;
+ clocks = <&clkuart2>;
interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
};
- uart3: serial@02348800 {
+ uart3: serial@2348800 {
compatible = "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02348800 0x100>;
- clocks = <&clkuart3>;
+ clocks = <&clkuart3>;
interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
};
};
mdio: mdio@26200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x26200f00 0x100>;
status = "disabled";
clocks = <&clkcpgmac>;
clock-names = "fck";
- bus_freq = <2500000>;
+ bus_freq = <2500000>;
};
/include/ "keystone-k2l-netcp.dtsi"
};
/include/ "keystone-clocks.dtsi"
- uart0: serial@02530c00 {
+ uart0: serial@2530c00 {
compatible = "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02530c00 0x100>;
- clocks = <&clkuart0>;
+ clocks = <&clkuart0>;
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
};
- uart1: serial@02531000 {
+ uart1: serial@2531000 {
compatible = "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02531000 0x100>;
- clocks = <&clkuart1>;
+ clocks = <&clkuart1>;
interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
};
dma-ranges;
status = "disabled";
- dwc3@2690000 {
+ usb@2690000 {
compatible = "synopsys,dwc3";
reg = <0x2690000 0x70000>;
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
};
};
- wdt: wdt@022f0080 {
+ wdt: wdt@22f0080 {
compatible = "ti,keystone-wdt","ti,davinci-wdt";
reg = <0x022f0080 0x80>;
clocks = <&clkwdtimer0>;
clock-names = "pcie";
#address-cells = <3>;
#size-cells = <2>;
- reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+ reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
ranges = <0x81000000 0 0 0x23250000 0 0x4000
0x82000000 0 0x50000000 0x50000000 0 0x10000000>;