u32 cpu_pwr_csr; /* offset 0x38 */
u32 mpid; /* offset 0x3c */
u32 ram_repair; /* offset 0x40 */
- u32 flow_dbg_sel; /* offset 0x44 */
- u32 flow_dbg_cnt0; /* offset 0x48 */
- u32 flow_dbg_cnt1; /* offset 0x4c */
- u32 flow_dbg_qual; /* offset 0x50 */
- u32 flow_ctlr_spare; /* offset 0x54 */
- u32 ram_repair_cluster1;/* offset 0x58 */
};
/* HALT_COP_EVENTS_0, 0x04 */
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
-/* RAM_REPAIR, 0x40, 0x58 */
-enum {
- RAM_REPAIR_REQ = 0x1 << 0,
- RAM_REPAIR_STS = 0x1 << 1,
-};
-
#endif /* _TEGRA124_FLOW_H_ */
#include <asm/io.h>
#include <asm/types.h>
-#include <asm/arch/flow.h>
+
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
return 0;
}
-static void tegra_powergate_ram_repair(void)
-{
-#ifdef CONFIG_TEGRA124
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
- /* Request RAM repair for cluster 0 and wait until complete */
- setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
- ;
-
- /* Same for cluster 1 */
- setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
- ;
-#endif
-}
-
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
- tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);