MSCC: Add device tree for Jaguar2 board

Add device tree based on evaluation board pcb110.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 2881d9e1f8e728520e1fe7352de9315f1162637c..c419bee8d2bf3f46340bed1da634faa069eb49a5 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -521,6 +521,7 @@ F:  arch/mips/mach-mscc/
 F:     arch/mips/dts/luton*
 F:     arch/mips/dts/mscc*
 F:     arch/mips/dts/ocelot*
+F:     arch/mips/dts/jr2*
 F:     board/mscc/
 F:     configs/mscc*
 F:     drivers/gpio/mscc_sgpio.c

diff --git a/arch/mips/dts/jr2_pcb110.dts b/arch/mips/dts/jr2_pcb110.dts
new file mode 100644 (file)
index 0000000..ddc30ff
--- /dev/null
+++ b/arch/mips/dts/jr2_pcb110.dts
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,jr2.dtsi"
+
+/ {
+       model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
+       compatible = "mscc,jr2-pcb110", "mscc,jr2";
+
+       aliases {
+               spi0 = &spi0;
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               status_green {
+                       label = "pcb110:green:status";
+                       gpios = <&gpio 12 0>;
+                       default-state = "on";
+               };
+
+               status_red {
+                       label = "pcb110:red:status";
+                       gpios = <&gpio 13 0>;
+                       default-state = "off";
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+       spi-flash@0 {
+               compatible = "spi-flash";
+               spi-max-frequency = <18000000>; /* input clock */
+               reg = <0>; /* CS0 */
+       };
+};
+
+&gpio {
+       /* SPIO only use DO, CLK, no inputs */
+       sgpio1_pins: sgpio1-pins {
+               pins = "GPIO_4", "GPIO_5";
+               function = "sg1";
+       };
+};
+
+&sgpio {
+       status = "okay";
+       sgpio-ports = <0x00ffffff>;
+};
+
+&sgpio1 {
+       status = "okay";
+       sgpio-ports = <0x00ff0000>;
+};
+
+&sgpio2 {
+       status = "okay";
+       sgpio-ports = <0x3f00ffff>;
+       gpio-ranges = <&sgpio2 0 0 96>;
+};

diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
new file mode 100644 (file)
index 0000000..0900926
--- /dev/null
+++ b/arch/mips/dts/mscc,jr2.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "mscc,jr2";
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "mips,mips24KEc";
+                       device_type = "cpu";
+                       clocks = <&cpu_clk>;
+                       reg = <0>;
+               };
+       };
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       cpuintc: interrupt-controller@0 {
+               #address-cells = <0>;
+               #interrupt-cells = <1>;
+               interrupt-controller;
+               compatible = "mti,cpu-interrupt-controller";
+       };
+
+       cpu_clk: cpu-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <500000000>;
+       };
+
+       ahb_clk: ahb-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <250000000>;
+       };
+
+       ahb {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x70000000 0x2000000>;
+
+               interrupt-parent = <&intc>;
+
+               cpu_ctrl: syscon@0 {
+                       compatible = "mscc,jr2-cpu-syscon", "syscon";
+                       reg = <0x0 0x2c>;
+               };
+
+               intc: interrupt-controller@70 {
+                       compatible = "mscc,jr2-icpu-intr";
+                       reg = <0x70 0x94>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+                       interrupt-parent = <&cpuintc>;
+                       interrupts = <2>;
+               };
+
+               uart0: serial@100000 {
+                       pinctrl-0 = <&uart_pins>;
+                       pinctrl-names = "default";
+                       compatible = "ns16550a";
+                       reg = <0x100000 0x20>;
+                       interrupts = <6>;
+                       clocks = <&ahb_clk>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+
+                       status = "disabled";
+               };
+
+               uart2: serial@100800 {
+                       pinctrl-0 = <&uart2_pins>;
+                       pinctrl-names = "default";
+                       compatible = "ns16550a";
+                       reg = <0x100800 0x20>;
+                       interrupts = <7>;
+                       clocks = <&ahb_clk>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+
+                       status = "disabled";
+               };
+
+               spi0: spi-master@101000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-ssi";
+                       reg = <0x101000 0x40>;
+                       num-chipselect = <4>;
+                       bus-num = <0>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       spi-max-frequency = <18000000>; /* input clock */
+                       clocks = <&ahb_clk>;
+
+                       status = "disabled";
+               };
+
+               reset@1010008 {
+                       compatible = "mscc,jr2-chip-reset";
+                       reg = <0x1010008 0x4>;
+               };
+
+               gpio: pinctrl@1070034 {
+                       compatible = "mscc,jaguar2-pinctrl";
+                       reg = <0x1010038 0x90>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&gpio 0 0 64>;
+
+                       sgpio_pins: sgpio-pins {
+                               pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+                               function = "sg0";
+                       };
+
+                       sgpio1_pins: sgpio1-pins {
+                               pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
+                               function = "sg1";
+                       };
+
+                       sgpio2_pins: sgpio2-pins {
+                               pins = "GPIO_30", "GPIO_31",
+                                      "GPIO_32", "GPIO_33";
+                               function = "sg2";
+                       };
+
+                       uart_pins: uart-pins {
+                               pins = "GPIO_10", "GPIO_11";
+                               function = "uart";
+                       };
+
+                       uart2_pins: uart2-pins {
+                               pins = "GPIO_24", "GPIO_25";
+                               function = "uart2";
+                       };
+               };
+
+               sgpio: gpio@1010150 {
+                       compatible = "mscc,ocelot-sgpio";
+                       status = "disabled";
+                       pinctrl-0 = <&sgpio_pins>;
+                       pinctrl-names = "default";
+                       reg = <0x1010150 0x100>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&sgpio 0 0 64>;
+                       gpio-bank-name = "sgpio0_";
+                       sgpio-clock = <0x14>;
+               };
+
+               sgpio1: gpio@101025c {
+                       compatible = "mscc,ocelot-sgpio";
+                       status = "disabled";
+                       pinctrl-0 = <&sgpio1_pins>;
+                       pinctrl-names = "default";
+                       reg = <0x101025c 0x100>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&sgpio1 0 0 64>;
+                       gpio-bank-name = "sgpio1_";
+                       sgpio-clock = <0x14>;
+               };
+
+               sgpio2: gpio@1010368 {
+                       compatible = "mscc,ocelot-sgpio";
+                       status = "disabled";
+                       pinctrl-0 = <&sgpio2_pins>;
+                       pinctrl-names = "default";
+                       reg = <0x1010368 0x100>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&sgpio2 0 0 64>;
+                       gpio-bank-name = "sgpio2_";
+                       sgpio-clock = <0x14>;
+               };
+       };
+};