board: phytec: phycore_imx8mp: Add support for different RAM sizes

Add support for different RAM sizes and speed grades on the
phyCORE-i.MX8MP.
Add support for 1GB 1.5GHz, 1GB 2GHz, 4GB 1.5GHz,
4GB 2GHz and 8GB 2GHz RAM.
The RAM size and speed grade is detected by the information
stored in the EEPROM on the SoM.

Co-developed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Co-developed-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Co-developed-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>

diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c
index f2707b859606ca6e063b8ea514243d776c68e025..9984b6c260130592bd4137439dd5c8bc26ef7e99 100644 (file)
--- a/board/phytec/phycore_imx8mp/lpddr4_timing.c
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c
@@ -1839,3 +1839,156 @@ struct dram_timing_info dram_timing = {
        .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
        .fsp_table = { 3000, 400, 100, },
 };
+
+void set_dram_timings_2ghz_2gb(void)
+{
+       dram_timing.ddrc_cfg[3].val = 0x1323;
+       dram_timing.ddrc_cfg[4].val = 0x1e84800;
+       dram_timing.ddrc_cfg[5].val = 0x7a0118;
+       dram_timing.ddrc_cfg[8].val = 0xc00307a3;
+       dram_timing.ddrc_cfg[9].val = 0xc50000;
+       dram_timing.ddrc_cfg[10].val = 0xf4003f;
+       dram_timing.ddrc_cfg[11].val = 0xf30000;
+       dram_timing.ddrc_cfg[14].val = 0x2028222a;
+       dram_timing.ddrc_cfg[15].val = 0x8083f;
+       dram_timing.ddrc_cfg[16].val = 0xe0e000;
+       dram_timing.ddrc_cfg[17].val = 0x12040a12;
+       dram_timing.ddrc_cfg[18].val = 0x2050f0f;
+       dram_timing.ddrc_cfg[19].val = 0x1010009;
+       dram_timing.ddrc_cfg[20].val = 0x502;
+       dram_timing.ddrc_cfg[21].val = 0x20800;
+       dram_timing.ddrc_cfg[22].val = 0xe100002;
+       dram_timing.ddrc_cfg[23].val = 0x120;
+       dram_timing.ddrc_cfg[24].val = 0xc80064;
+       dram_timing.ddrc_cfg[25].val = 0x3e8001e;
+       dram_timing.ddrc_cfg[26].val = 0x3207a12;
+       dram_timing.ddrc_cfg[28].val = 0x4a3820e;
+       dram_timing.ddrc_cfg[30].val = 0x230e;
+       dram_timing.ddrc_cfg[37].val = 0x799;
+       dram_timing.ddrc_cfg[38].val = 0x9141d1c;
+       dram_timing.ddrc_cfg[74].val = 0x302;
+       dram_timing.ddrc_cfg[83].val = 0x599;
+       dram_timing.ddrc_cfg[99].val = 0x302;
+       dram_timing.ddrc_cfg[108].val = 0x599;
+       dram_timing.ddrphy_cfg[66].val = 0x18;
+       dram_timing.ddrphy_cfg[75].val = 0x1e3;
+       dram_timing.ddrphy_cfg[77].val = 0x1e3;
+       dram_timing.ddrphy_cfg[79].val = 0x1e3;
+       dram_timing.ddrphy_cfg[145].val = 0x3e8;
+       dram_timing.fsp_msg[0].drate = 4000;
+       dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
+       dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
+       dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+       dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
+       dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+       dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
+       dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
+       dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
+       dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
+       dram_timing.fsp_msg[3].drate = 4000;
+       dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
+       dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
+       dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+       dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
+       dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+       dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
+       dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
+       dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
+       dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
+       dram_timing.ddrphy_pie[480].val = 0x465;
+       dram_timing.ddrphy_pie[481].val = 0xfa;
+       dram_timing.ddrphy_pie[482].val = 0x9c4;
+       dram_timing.fsp_table[0] = 4000;
+}
+
+void set_dram_timings_1_5ghz_1gb(void)
+{
+       dram_timing.ddrc_cfg[3].val = 0x1233;
+       dram_timing.ddrc_cfg[5].val = 0x5b0087;
+       dram_timing.ddrc_cfg[6].val = 0x61027f10;
+       dram_timing.ddrc_cfg[7].val = 0x7b0;
+       dram_timing.ddrc_cfg[11].val = 0xf30000;
+       dram_timing.ddrc_cfg[23].val = 0x8d;
+       dram_timing.ddrc_cfg[45].val = 0xf070707;
+       dram_timing.ddrc_cfg[59].val = 0x1031;
+       dram_timing.ddrc_cfg[62].val = 0xc0012;
+       dram_timing.ddrc_cfg[77].val = 0x13;
+       dram_timing.ddrc_cfg[84].val = 0x1031;
+       dram_timing.ddrc_cfg[87].val = 0x30005;
+       dram_timing.ddrc_cfg[102].val = 0x5;
+       dram_timing.ddrphy_cfg[75].val = 0x1e3;
+       dram_timing.ddrphy_cfg[77].val = 0x1e3;
+       dram_timing.ddrphy_cfg[79].val = 0x1e3;
+       dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+       dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+       dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d;
+       dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d;
+       dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+       dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+       dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d;
+       dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d;
+}
+
+void set_dram_timings_2ghz_1gb(void)
+{
+       set_dram_timings_2ghz_2gb();
+       dram_timing.ddrc_cfg[5].val = 0x7a00b4;
+       dram_timing.ddrc_cfg[23].val = 0xbc;
+       dram_timing.ddrc_cfg[45].val = 0xf070707;
+       dram_timing.ddrc_cfg[62].val = 0xc0012;
+       dram_timing.ddrc_cfg[77].val = 0x13;
+       dram_timing.ddrc_cfg[87].val = 0x30005;
+       dram_timing.ddrc_cfg[102].val = 0x5;
+}
+
+void set_dram_timings_1_5ghz_4gb(void)
+{
+       dram_timing.ddrc_cfg[2].val = 0xa3080020;
+       dram_timing.ddrc_cfg[39].val = 0x17;
+       dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+       dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+       dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+       dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+       dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_4gb(void)
+{
+       set_dram_timings_2ghz_2gb();
+       dram_timing.ddrc_cfg[2].val = 0xa3080020;
+       dram_timing.ddrc_cfg[39].val = 0x17;
+       dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+       dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+       dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+       dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+       dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_8gb(void)
+{
+       set_dram_timings_2ghz_2gb();
+       dram_timing.ddrc_cfg[2].val = 0xa3080020;
+       dram_timing.ddrc_cfg[5].val = 0x7a017c;
+       dram_timing.ddrc_cfg[23].val = 0x184;
+       dram_timing.ddrc_cfg[39].val = 0x18;
+       dram_timing.ddrc_cfg[46].val = 0xf07;
+       dram_timing.ddrc_cfg[62].val = 0xc0026;
+       dram_timing.ddrc_cfg[77].val = 0x27;
+       dram_timing.ddrc_cfg[87].val = 0x3000a;
+       dram_timing.ddrc_cfg[102].val = 0xa;
+
+       dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+       dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+       dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+       dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+       dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+       dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}

diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.h b/board/phytec/phycore_imx8mp/lpddr4_timing.h
new file mode 100644 (file)
index 0000000..1c10e08
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void set_dram_timings_2ghz_2gb(void);
+void set_dram_timings_2ghz_1gb(void);
+void set_dram_timings_2ghz_4gb(void);
+void set_dram_timings_1_5ghz_1gb(void);
+void set_dram_timings_1_5ghz_4gb(void);
+void set_dram_timings_2ghz_8gb(void);
+
+#endif /* __LPDDR4_TIMING_H__ */

diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index 35683591433cfccf73484f353c072da479469615..ef9513618449157843b3061bbdb024a53f800298 100644 (file)
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <env.h>
+#include <init.h>
 #include <miiphy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -55,3 +56,13 @@ int board_late_init(void)
 
        return 0;
 }
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+       if (!size)
+               return -EINVAL;
+
+       *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+
+       return 0;
+}

diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index cffa0a57fe669a742367d555af5dc086b5f3f6fe..855aa1a9009e10bd68a29709f4664c58bb7ff9c2 100644 (file)
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -20,6 +20,7 @@
 #include <power/pca9450.h>
 #include <spl.h>
 
+#include "lpddr4_timing.h"
 #include "../common/imx8m_som_detection.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -32,9 +33,19 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
        return BOOT_DEVICE_BOOTROM;
 }
 
+enum phytec_imx8mp_ddr_eeprom_code {
+       PHYTEC_IMX8MP_DDR_1GB = 2,
+       PHYTEC_IMX8MP_DDR_2GB = 3,
+       PHYTEC_IMX8MP_DDR_4GB = 5,
+       PHYTEC_IMX8MP_DDR_8GB = 7,
+       PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8,
+};
+
 void spl_dram_init(void)
 {
        int ret;
+       bool use_2ghz_timings = false;
+       enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
 
        ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
                                                EEPROM_ADDR_FALLBACK);
@@ -48,67 +59,38 @@ void spl_dram_init(void)
        u8 rev = phytec_get_rev(NULL);
        u8 somtype = phytec_get_som_type(NULL);
 
-       if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) {
-               dram_timing.ddrc_cfg[3].val = 0x1323;
-               dram_timing.ddrc_cfg[4].val = 0x1e84800;
-               dram_timing.ddrc_cfg[5].val = 0x7a0118;
-               dram_timing.ddrc_cfg[8].val = 0xc00307a3;
-               dram_timing.ddrc_cfg[9].val = 0xc50000;
-               dram_timing.ddrc_cfg[10].val = 0xf4003f;
-               dram_timing.ddrc_cfg[11].val = 0xf30000;
-               dram_timing.ddrc_cfg[14].val = 0x2028222a;
-               dram_timing.ddrc_cfg[15].val = 0x8083f;
-               dram_timing.ddrc_cfg[16].val = 0xe0e000;
-               dram_timing.ddrc_cfg[17].val = 0x12040a12;
-               dram_timing.ddrc_cfg[18].val = 0x2050f0f;
-               dram_timing.ddrc_cfg[19].val = 0x1010009;
-               dram_timing.ddrc_cfg[20].val = 0x502;
-               dram_timing.ddrc_cfg[21].val = 0x20800;
-               dram_timing.ddrc_cfg[22].val = 0xe100002;
-               dram_timing.ddrc_cfg[23].val = 0x120;
-               dram_timing.ddrc_cfg[24].val = 0xc80064;
-               dram_timing.ddrc_cfg[25].val = 0x3e8001e;
-               dram_timing.ddrc_cfg[26].val = 0x3207a12;
-               dram_timing.ddrc_cfg[28].val = 0x4a3820e;
-               dram_timing.ddrc_cfg[30].val = 0x230e;
-               dram_timing.ddrc_cfg[37].val = 0x799;
-               dram_timing.ddrc_cfg[38].val = 0x9141d1c;
-               dram_timing.ddrc_cfg[74].val = 0x302;
-               dram_timing.ddrc_cfg[83].val = 0x599;
-               dram_timing.ddrc_cfg[99].val = 0x302;
-               dram_timing.ddrc_cfg[108].val = 0x599;
-               dram_timing.ddrphy_cfg[66].val = 0x18;
-               dram_timing.ddrphy_cfg[75].val = 0x1e3;
-               dram_timing.ddrphy_cfg[77].val = 0x1e3;
-               dram_timing.ddrphy_cfg[79].val = 0x1e3;
-               dram_timing.ddrphy_cfg[145].val = 0x3e8;
-               dram_timing.fsp_msg[0].drate = 4000;
-               dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
-               dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
-               dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
-               dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
-               dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
-               dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
-               dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
-               dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
-               dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
-               dram_timing.fsp_msg[3].drate = 4000;
-               dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
-               dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
-               dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
-               dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
-               dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
-               dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
-               dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
-               dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
-               dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
-               dram_timing.ddrphy_pie[480].val = 0x465;
-               dram_timing.ddrphy_pie[481].val = 0xfa;
-               dram_timing.ddrphy_pie[482].val = 0x9c4;
-               dram_timing.fsp_table[0] = 4000;
+       if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
+               use_2ghz_timings = true;
+
+       size = phytec_get_imx8m_ddr_size(NULL);
+
+       switch (size) {
+       case PHYTEC_IMX8MP_DDR_1GB:
+               if (use_2ghz_timings)
+                       set_dram_timings_2ghz_1gb();
+               else
+                       set_dram_timings_1_5ghz_1gb();
+               break;
+       case PHYTEC_IMX8MP_DDR_2GB:
+               if (use_2ghz_timings)
+                       set_dram_timings_2ghz_2gb();
+               break;
+       case PHYTEC_IMX8MP_DDR_4GB:
+               set_dram_timings_1_5ghz_4gb();
+               break;
+       case PHYTEC_IMX8MP_DDR_4GB_2GHZ:
+               set_dram_timings_2ghz_4gb();
+               break;
+       case PHYTEC_IMX8MP_DDR_8GB:
+               set_dram_timings_2ghz_8gb();
+               break;
+       default:
+               goto out;
        }
-
+       ddr_init(&dram_timing);
+       return;
 out:
+       printf("Could not detect correct RAM size. Fallback to default.\n");
        ddr_init(&dram_timing);
 }
 

diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 206c4d50d2767dd860cceecf518e77931b942aeb..299fabc6a99bcb1410b926851b20a0e3ce3bbb19 100644 (file)
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -22,6 +22,8 @@
 #define CFG_SYS_SDRAM_BASE             0x40000000
 
 #define PHYS_SDRAM                     0x40000000
-#define PHYS_SDRAM_SIZE                        0x80000000
+#define PHYS_SDRAM_SIZE                 (SZ_2G + SZ_1G) /* 3GB */
+#define PHYS_SDRAM_2                    0x100000000
+#define PHYS_SDRAM_2_SIZE               (SZ_4G + SZ_1G) /* 5GB */
 
 #endif /* __PHYCORE_IMX8MP_H */