Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot...

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location

diff --cc MAINTAINERS
Simple merge

diff --cc Makefile
Simple merge

diff --cc arch/Kconfig
Simple merge

diff --cc arch/arm/dts/Makefile
Simple merge

diff --cc arch/m68k/Kconfig
Simple merge

diff --cc arch/microblaze/cpu/start.S
index 25e9968e4c65a2edcafde6e0d6d4a47e9edce88e,de952701dfffe385670d54c22d5ba67c1878e8fb..a877db305e4ca61cd68a4003fde307e5d1e6b819
--- 1/arch/microblaze/cpu/start.S
--- 2/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@@ -14,14 -25,49 +25,49 @@@
        .global _start
  _start:
        mts     rmsr, r0        /* disable cache */
+       mfs     r20, rpc
+       addi    r20, r20, -4
  
-       addi    r8, r0, _end
-       mts     rslr, r8
+       mts     rslr, r0
+       mts     rshr, r20
  
  #if defined(CONFIG_SPL_BUILD)
 -      addi    r1, r0, CONFIG_SPL_STACK_ADDR
 +      addi    r1, r0, CONFIG_SPL_STACK
  #else
-       addi    r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+       add     r1, r0, r20
+ #if defined(CONFIG_STATIC_RELA)
+       bri     1f
+ 
+       /* Force alignment for easier ASM code below */
+ #define ALIGNMENT_ADDR        0x20
+       .align  4
+ uboot_dyn_start:
+       .word   __rel_dyn_start
+ 
+ uboot_dyn_end:
+       .word   __rel_dyn_end
+ 
+ uboot_sym_start:
+       .word   __dyn_sym_start
+ 1:
+ 
+       addi    r5, r20, 0
+       add     r6, r0, r0
+ 
+       lwi     r7, r20, ALIGNMENT_ADDR
+       addi    r7, r7, -CONFIG_SYS_TEXT_BASE
+       add     r7, r7, r5
+       lwi     r8, r20, ALIGNMENT_ADDR + 0x4
+       addi    r8, r8, -CONFIG_SYS_TEXT_BASE
+       add     r8, r8, r5
+       lwi     r9, r20, ALIGNMENT_ADDR + 0x8
+       addi    r9, r9, -CONFIG_SYS_TEXT_BASE
+       add     r9, r9, r5
+       addi    r10, r0, CONFIG_SYS_TEXT_BASE
+ 
+       brlid   r15, mb_fix_rela
+       nop
+ #endif
  #endif
  
        addi    r1, r1, -4      /* Decrement SP to top of memory */

diff --cc arch/microblaze/cpu/u-boot.lds
Simple merge

diff --cc configs/microblaze-generic_defconfig
Simple merge

diff --cc configs/xilinx_versal_virt_defconfig
Simple merge

diff --cc configs/xilinx_zynq_virt_defconfig
Simple merge

diff --cc configs/xilinx_zynqmp_virt_defconfig
Simple merge

diff --cc drivers/core/device.c
Simple merge

diff --cc drivers/timer/Kconfig
Simple merge

diff --cc drivers/timer/Makefile
Simple merge

diff --cc include/configs/microblaze-generic.h
index 2adc1f6d86b88d855b81f33a3663151c0c77075a,bae0f284fdca73ce3e07d857227348e0516d4224..af6c728790c699a8e3577e86e74b3f11f60ff8f5
--- 1/include/configs/microblaze-generic.h
--- 2/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@@ -30,10 -26,11 +26,6 @@@
  # define CONFIG_SYS_MAX_FLASH_SECT    2048
  #endif
  
- #ifndef XILINX_DCACHE_BYTE_SIZE
- #define XILINX_DCACHE_BYTE_SIZE       32768
- #endif
 -/* size of console buffer */
 -#define       CONFIG_SYS_CBSIZE       512
 -/* max number of command args */
 -#define       CONFIG_SYS_MAXARGS      15
--
  #define       CONFIG_HOSTNAME         "microblaze-generic"
  
  /* architecture dependent code */