#ifndef _MACH_STM32_H_
#define _MACH_STM32_H_
++#include <linux/sizes.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
+
+ enum boot_device {
+ BOOT_FLASH_SD = 0x10,
+ BOOT_FLASH_SD_1 = 0x11,
+ BOOT_FLASH_SD_2 = 0x12,
+ BOOT_FLASH_SD_3 = 0x13,
+
+ BOOT_FLASH_EMMC = 0x20,
+ BOOT_FLASH_EMMC_1 = 0x21,
+ BOOT_FLASH_EMMC_2 = 0x22,
+ BOOT_FLASH_EMMC_3 = 0x23,
+
+ BOOT_FLASH_NAND = 0x30,
+ BOOT_FLASH_NAND_FMC = 0x31,
+
+ BOOT_FLASH_NOR = 0x40,
+ BOOT_FLASH_NOR_QSPI = 0x41,
+
+ BOOT_SERIAL_UART = 0x50,
+ BOOT_SERIAL_UART_1 = 0x51,
+ BOOT_SERIAL_UART_2 = 0x52,
+ BOOT_SERIAL_UART_3 = 0x53,
+ BOOT_SERIAL_UART_4 = 0x54,
+ BOOT_SERIAL_UART_5 = 0x55,
+ BOOT_SERIAL_UART_6 = 0x56,
+ BOOT_SERIAL_UART_7 = 0x57,
+ BOOT_SERIAL_UART_8 = 0x58,
+
+ BOOT_SERIAL_USB = 0x60,
+ BOOT_SERIAL_USB_OTG = 0x62,
+
+ BOOT_FLASH_SPINAND = 0x70,
+ BOOT_FLASH_SPINAND_1 = 0x71,
+ };
+
+ #define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
+ #define TAMP_BOOT_MODE_SHIFT 8
+ #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
+ #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+ #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+ #define TAMP_BOOT_DEBUG_ON BIT(16)
+
+ enum forced_boot_mode {
+ BOOT_NORMAL = 0x00,
+ BOOT_FASTBOOT = 0x01,
+ BOOT_RECOVERY = 0x02,
+ BOOT_STM32PROG = 0x03,
+ BOOT_UMS_MMC0 = 0x10,
+ BOOT_UMS_MMC1 = 0x11,
+ BOOT_UMS_MMC2 = 0x12,
+ };
+
#endif
/*
--- /dev/null
-#include <common.h>
+ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+ #include <asm/system.h>
+ #include <asm/armv8/mmu.h>
++#include <mach/stm32.h>
+
+ #define MP2_MEM_MAP_MAX 10
+
+ #if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
+ (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
+ #error "invalid CONFIG_TEXT_BASE value"
+ #endif
+
+ struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
+ {
+ /* PCIe */
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0x00200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Peripherals: alias1 */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* OSPI and FMC: memory-map area */
+ .virt = 0x60000000UL,
+ .phys = 0x60000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /*
+ * DDR = STM32_DDR_BASE / STM32_DDR_SIZE
+ * the beginning of DDR (before CONFIG_TEXT_BASE) is not
+ * mapped, protected by RIF and reserved for other firmware
+ * (OP-TEE / TF-M / Cube M33)
+ */
+ .virt = CONFIG_TEXT_BASE,
+ .phys = CONFIG_TEXT_BASE,
+ .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+ };
+
+ struct mm_region *mem_map = stm32mp2_mem_map;
--- /dev/null
-#include <common.h>
+ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+ #define LOG_CATEGORY LOGC_ARCH
+
+ #include <clk.h>
+ #include <cpu_func.h>
+ #include <debug_uart.h>
+ #include <env_internal.h>
+ #include <init.h>
+ #include <misc.h>
+ #include <wdt.h>
+ #include <asm/io.h>
+ #include <asm/arch/stm32.h>
+ #include <asm/arch/sys_proto.h>
+ #include <asm/system.h>
+ #include <dm/device.h>
+ #include <dm/lists.h>
+ #include <dm/uclass.h>
+
+ /*
+ * early TLB into the .data section so that it not get cleared
+ * with 16kB alignment
+ */
+ #define EARLY_TLB_SIZE 0xA000
+ u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
+
+ /*
+ * initialize the MMU and activate cache in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ */
+ static void early_enable_caches(void)
+ {
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+ gd->arch.tlb_size = EARLY_TLB_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ }
+ /* enable MMU (default configuration) */
+ dcache_enable();
+ }
+
+ /*
+ * Early system init
+ */
+ int arch_cpu_init(void)
+ {
+ icache_enable();
+ early_enable_caches();
+
+ return 0;
+ }
+
+ void enable_caches(void)
+ {
+ /* deactivate the data cache, early enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
+ * to update the TLB location udpated in board_f.c::reserve_mmu
+ */
+ gd->arch.tlb_fillptr = 0;
+ dcache_enable();
+ }
+
+ /* used when CONFIG_DISPLAY_CPUINFO is activated */
+ int print_cpuinfo(void)
+ {
+ char name[SOC_NAME_SIZE];
+
+ get_soc_name(name);
+ printf("CPU: %s\n", name);
+
+ return 0;
+ }
+
+ int arch_misc_init(void)
+ {
+ return 0;
+ }
+
+ /*
+ * Force data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+ static uintptr_t nt_fw_dtb __section(".data");
+
+ uintptr_t get_stm32mp_bl2_dtb(void)
+ {
+ return nt_fw_dtb;
+ }
+
+ /*
+ * Save the FDT address provided by TF-A in r2 at boot time
+ * This function is called from start.S
+ */
+ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
+ {
+ nt_fw_dtb = r2;
+
+ save_boot_params_ret();
+ }
--- /dev/null
-#include <common.h>
+ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
++#include <asm/u-boot.h>
+
+ /*
+ * This function is called right before the kernel is booted. "blob" is the
+ * device tree that will be passed to the kernel.
+ */
+ int ft_system_setup(void *blob, struct bd_info *bd)
+ {
+ return 0;
+ }
+
--- /dev/null
-#include <common.h>
+ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+ #define LOG_CATEGORY LOGC_ARCH
+
+ #include <log.h>
+ #include <syscon.h>
+ #include <asm/io.h>
+ #include <asm/arch/stm32.h>
+ #include <asm/arch/sys_proto.h>
+
+ /* SYSCFG register */
+ #define SYSCFG_DEVICEID_OFFSET 0x6400
+ #define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
+ #define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
+ #define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
+ #define SYSCFG_DEVICEID_REV_ID_SHIFT 16
+
+ /* Device Part Number (RPN) = OTP9 */
+ #define RPN_SHIFT 0
+ #define RPN_MASK GENMASK(31, 0)
+
+ /* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
+ * - 000: Custom package
+ * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
+ * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
+ * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
+ * - others: Reserved
+ */
+ #define PKG_SHIFT 0
+ #define PKG_MASK GENMASK(2, 0)
+
+ static u32 read_deviceid(void)
+ {
+ void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
+ }
+
+ u32 get_cpu_dev(void)
+ {
+ return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
+ }
+
+ u32 get_cpu_rev(void)
+ {
+ return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
+ }
+
+ /* Get Device Part Number (RPN) from OTP */
+ u32 get_cpu_type(void)
+ {
+ return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+ }
+
+ /* Get Package options from OTP */
+ u32 get_cpu_package(void)
+ {
+ return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
+ }
+
+ int get_eth_nb(void)
+ {
+ int nb_eth;
+
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ fallthrough;
+ case CPU_STM32MP257Dxx:
+ fallthrough;
+ case CPU_STM32MP257Cxx:
+ fallthrough;
+ case CPU_STM32MP257Axx:
+ nb_eth = 5; /* dual ETH with TSN support */
+ break;
+ case CPU_STM32MP253Fxx:
+ fallthrough;
+ case CPU_STM32MP253Dxx:
+ fallthrough;
+ case CPU_STM32MP253Cxx:
+ fallthrough;
+ case CPU_STM32MP253Axx:
+ nb_eth = 2; /* dual ETH */
+ break;
+ case CPU_STM32MP251Fxx:
+ fallthrough;
+ case CPU_STM32MP251Dxx:
+ fallthrough;
+ case CPU_STM32MP251Cxx:
+ fallthrough;
+ case CPU_STM32MP251Axx:
+ nb_eth = 1; /* single ETH */
+ break;
+ default:
+ nb_eth = 0;
+ break;
+ }
+
+ return nb_eth;
+ }
+
+ void get_soc_name(char name[SOC_NAME_SIZE])
+ {
+ char *cpu_s, *cpu_r, *package;
+
+ cpu_s = "????";
+ cpu_r = "?";
+ package = "??";
+ if (get_cpu_dev() == CPU_DEV_STM32MP25) {
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ cpu_s = "257F";
+ break;
+ case CPU_STM32MP257Dxx:
+ cpu_s = "257D";
+ break;
+ case CPU_STM32MP257Cxx:
+ cpu_s = "257C";
+ break;
+ case CPU_STM32MP257Axx:
+ cpu_s = "257A";
+ break;
+ case CPU_STM32MP255Fxx:
+ cpu_s = "255F";
+ break;
+ case CPU_STM32MP255Dxx:
+ cpu_s = "255D";
+ break;
+ case CPU_STM32MP255Cxx:
+ cpu_s = "255C";
+ break;
+ case CPU_STM32MP255Axx:
+ cpu_s = "255A";
+ break;
+ case CPU_STM32MP253Fxx:
+ cpu_s = "253F";
+ break;
+ case CPU_STM32MP253Dxx:
+ cpu_s = "253D";
+ break;
+ case CPU_STM32MP253Cxx:
+ cpu_s = "253C";
+ break;
+ case CPU_STM32MP253Axx:
+ cpu_s = "253A";
+ break;
+ case CPU_STM32MP251Fxx:
+ cpu_s = "251F";
+ break;
+ case CPU_STM32MP251Dxx:
+ cpu_s = "251D";
+ break;
+ case CPU_STM32MP251Cxx:
+ cpu_s = "251C";
+ break;
+ case CPU_STM32MP251Axx:
+ cpu_s = "251A";
+ break;
+ default:
+ cpu_s = "25??";
+ break;
+ }
+ /* REVISION */
+ switch (get_cpu_rev()) {
+ case CPU_REV1:
+ cpu_r = "A";
+ break;
+ default:
+ break;
+ }
+ /* PACKAGE */
+ switch (get_cpu_package()) {
+ case STM32MP25_PKG_CUSTOM:
+ package = "XX";
+ break;
+ case STM32MP25_PKG_AL_TBGA361:
+ package = "AL";
+ break;
+ case STM32MP25_PKG_AK_TBGA424:
+ package = "AK";
+ break;
+ case STM32MP25_PKG_AI_TBGA436:
+ package = "AI";
+ break;
+ default:
+ break;
+ }
+ }
+
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
+ }
--- /dev/null
-#include <common.h>
+ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+ #define LOG_CATEGORY LOGC_BOARD
+
+ #include <config.h>
+ #include <env.h>
+ #include <fdt_support.h>
+ #include <asm/global_data.h>
+ #include <asm/arch/sys_proto.h>
+
+ /*
+ * Get a global data pointer
+ */
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* board dependent setup after realloc */
+ int board_init(void)
+ {
+ return 0;
+ }
+
+ int board_late_init(void)
+ {
+ const void *fdt_compat;
+ int fdt_compat_len;
+ char dtb_name[256];
+ int buf_len;
+
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+ &fdt_compat_len);
+ if (fdt_compat && fdt_compat_len) {
+ if (strncmp(fdt_compat, "st,", 3) != 0) {
+ env_set("board_name", fdt_compat);
+ } else {
+ env_set("board_name", fdt_compat + 3);
+
+ buf_len = sizeof(dtb_name);
+ strlcpy(dtb_name, fdt_compat + 3, buf_len);
+ buf_len -= strlen(fdt_compat + 3);
+ strlcat(dtb_name, ".dtb", buf_len);
+ env_set("fdtfile", dtb_name);
+ }
+ }
+ }
+
+ return 0;
+ }
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