arm: at91/spl: matrix: use matrix slave id macros

To make matrix initialization code sharing with others,
use the matrix slave id macros, instead of hard-coding.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>

diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 3da8aff27ee6ce154b138aaf935884da737dfa3c..449cf0ede3b2703c34670d4813f07faa4796693c 100644 (file)
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -179,6 +179,31 @@
 #define CPU_HAS_PCR
 #define CPU_HAS_H32MXDIV
 
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE       0       /* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE      1       /* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_VDEC               2       /* Video Decoder */
+#define H64MX_SLAVE_DDRC_PORT0         3       /* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1         4       /* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2         5       /* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3         6       /* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4         7       /* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5         8       /* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6         9       /* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7         10      /* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM               11      /* Internal SRAM 128K */
+#define H64MX_SLAVE_H32MX_BRIDGE       12      /* Bridge from H64MX to H32MX */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE       0       /* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0     1       /* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1     2       /* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI                        3       /* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD            3       /* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM           4       /* NFC SRAM */
+#define H32MX_SLAVE_USB                        5       /* USB Device & Host */
+#define H32MX_SLAVE_SMD                        6       /* Soft Modem (SMD) */
+
 /* sama5d4 series chip id definitions */
 #define ARCH_ID_SAMA5D4                0x8a5c07c0
 #define ARCH_EXID_SAMA5D41     0x00000001

diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
index e4780d62df6ca510b8e0e3eb161407a95642d0a8..57d72700d330e00e92f54ab074976ea7ad866511 100644 (file)
--- a/arch/arm/mach-at91/matrix.c
+++ b/arch/arm/mach-at91/matrix.c
@@ -15,20 +15,20 @@ void matrix_init(void)
        struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
        int i;
 
-       /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
-       for (i = 4; i <= 10; i++) {
+       /* DDR port 1 ~ port 7 */
+       for (i = H64MX_SLAVE_DDRC_PORT1; i <= H64MX_SLAVE_DDRC_PORT7; i++) {
                writel(0x000f0f0f, &h64mx->ssr[i]);
                writel(0x0000ffff, &h64mx->sassr[i]);
                writel(0x0000000f, &h64mx->srtsr[i]);
        }
 
-       /* CS3 */
-       writel(0x00c0c0c0, &h32mx->ssr[3]);
-       writel(0xff000000, &h32mx->sassr[3]);
-       writel(0xff000000, &h32mx->srtsr[3]);
+       /* EBI CS3 (NANDFlash 128M) and NFC Command Registers(128M) */
+       writel(0x00c0c0c0, &h32mx->ssr[H32MX_SLAVE_EBI]);
+       writel(0xff000000, &h32mx->sassr[H32MX_SLAVE_EBI]);
+       writel(0xff000000, &h32mx->srtsr[H32MX_SLAVE_EBI]);
 
        /* NFC SRAM */
-       writel(0x00010101, &h32mx->ssr[4]);
-       writel(0x00000001, &h32mx->sassr[4]);
-       writel(0x00000001, &h32mx->srtsr[4]);
+       writel(0x00010101, &h32mx->ssr[H32MX_SLAVE_NFC_SRAM]);
+       writel(0x00000001, &h32mx->sassr[H32MX_SLAVE_NFC_SRAM]);
+       writel(0x00000001, &h32mx->srtsr[H32MX_SLAVE_NFC_SRAM]);
 }