mmc: omap_hsmmc: reset FSM for DAT and CMD lines if needed before a new command

It sometimes happen that the PSTATE register does not indicate that the
bus is ready when it really is. This usually happens after a mode switch.
In that case it makes sense to reset the FSM handling the CMD and DATA

Also reset the FSMs if the STATE register cannot be cleared. This also
sometimes happens after a mode switch.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 133cdc135278884798ddd8c83f0012c516704437..5446ca8b8d7a6b19e5e0eaa6533042d32a8c00c2 100644 (file)
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -1065,18 +1065,17 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
                if (get_timer(0) - start > MAX_RETRY_MS) {
                        printf("%s: timedout waiting on cmd inhibit to clear\n",
                                        __func__);
+                       mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+                       mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
                        return -ETIMEDOUT;
                }
        }
        writel(0xFFFFFFFF, &mmc_base->stat);
-       start = get_timer(0);
-       while (readl(&mmc_base->stat)) {
-               if (get_timer(0) - start > MAX_RETRY_MS) {
-                       printf("%s: timedout waiting for STAT (%x) to clear\n",
-                               __func__, readl(&mmc_base->stat));
-                       return -ETIMEDOUT;
-               }
+       if (readl(&mmc_base->stat)) {
+               mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+               mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
        }
+
        /*
         * CMDREG
         * CMDIDX[13:8] : Command index