pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9

Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index de22e49ebef4bcc4930ce9dcc6774a6874ea80a7..b13fc0ba632943c3c15d9ab687019adc0420bb10 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -217,8 +217,8 @@
 #define IP2_11_8       FM(AVB_MDC)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2_15_12      FM(BS_N)                FM(PWM0_A)              FM(AVB_MAGIC)           FM(VI4_CLK)             F_(0, 0)                FM(TX3_C)       F_(0, 0)        FM(VI5_CLK_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2_19_16      FM(RD_N)                FM(PWM1_A)              FM(AVB_LINK)            FM(VI4_FIELD)           F_(0, 0)                FM(RX3_C)       FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20      FM(RD_WR_N)             FM(SCL7_A)              FM(AVB_AVTP_MATCH_A)    FM(VI4_VSYNC_N)         FM(TX5_B)               FM(SCK3_C)      FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24      FM(EX_WAIT0)            FM(SDA7_A)              FM(AVB_AVTP_CAPTURE_A)  FM(VI4_HSYNC_N)         FM(RX5_B)               FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20      FM(RD_WR_N)             FM(SCL7_A)              FM(AVB_AVTP_MATCH)      FM(VI4_VSYNC_N)         FM(TX5_B)               FM(SCK3_C)      FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24      FM(EX_WAIT0)            FM(SDA7_A)              FM(AVB_AVTP_CAPTURE)    FM(VI4_HSYNC_N)         FM(RX5_B)               FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2_31_28      FM(A0)                  FM(IRQ0)                FM(PWM2_A)              FM(MSIOF3_SS1_B)        FM(VI5_CLK_A)           FM(DU_CDE)      FM(HRX3_D)      FM(IERX)        FM(QSTB_QHE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3_3_0                FM(A1)                  FM(IRQ1)                FM(PWM3_A)              FM(DU_DOTCLKIN1)        FM(VI5_DATA0_A)         FM(DU_DISP_CDE) FM(SDA6_B)      FM(IETX)        FM(QCPV_QDE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3_7_4                FM(A2)                  FM(IRQ2)                FM(AVB_AVTP_PPS)        FM(VI4_CLKENB)          FM(VI5_DATA1_A)         FM(DU_DISP)     FM(SCL6_B)      F_(0, 0)        FM(QSTVB_QVE)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -433,6 +433,8 @@ FM(IP12_31_28)      IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM
 #define MOD_SEL0_1_0      REV4(FM(SEL_SPEED_PULSE_IF_0),       FM(SEL_SPEED_PULSE_IF_1),       FM(SEL_SPEED_PULSE_IF_2),       F_(0, 0))
 
 /* MOD_SEL1 */                 /* 0 */                         /* 1 */                         /* 2 */                         /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */
+#define MOD_SEL1_31            FM(SEL_SIMCARD_0)               FM(SEL_SIMCARD_1)
+#define MOD_SEL1_30            FM(SEL_SSI2_0)                  FM(SEL_SSI2_1)
 #define MOD_SEL1_29            FM(SEL_TIMER_TMU_0)             FM(SEL_TIMER_TMU_1)
 #define MOD_SEL1_28            FM(SEL_USB_20_CH0_0)            FM(SEL_USB_20_CH0_1)
 #define MOD_SEL1_26            FM(SEL_DRIF2_0)                 FM(SEL_DRIF2_1)
@@ -453,7 +455,8 @@ FM(IP12_31_28)      IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM
 
 #define PINMUX_MOD_SELS        \
 \
-MOD_SEL0_30_29 \
+                       MOD_SEL1_31 \
+MOD_SEL0_30_29         MOD_SEL1_30 \
                        MOD_SEL1_29 \
 MOD_SEL0_28            MOD_SEL1_28 \
 MOD_SEL0_27_26 \
@@ -619,7 +622,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP2_23_20,             RD_WR_N),
        PINMUX_IPSR_MSEL(IP2_23_20,             SCL7_A,         SEL_I2C7_0),
-       PINMUX_IPSR_GPSR(IP2_23_20,             AVB_AVTP_MATCH_A),
+       PINMUX_IPSR_GPSR(IP2_23_20,             AVB_AVTP_MATCH),
        PINMUX_IPSR_GPSR(IP2_23_20,             VI4_VSYNC_N),
        PINMUX_IPSR_GPSR(IP2_23_20,             TX5_B),
        PINMUX_IPSR_MSEL(IP2_23_20,             SCK3_C,         SEL_SCIF3_2),
@@ -627,7 +630,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP2_27_24,             EX_WAIT0),
        PINMUX_IPSR_MSEL(IP2_27_24,             SDA7_A,         SEL_I2C7_0),
-       PINMUX_IPSR_GPSR(IP2_27_24,             AVB_AVTP_CAPTURE_A),
+       PINMUX_IPSR_GPSR(IP2_27_24,             AVB_AVTP_CAPTURE),
        PINMUX_IPSR_GPSR(IP2_27_24,             VI4_HSYNC_N),
        PINMUX_IPSR_MSEL(IP2_27_24,             RX5_B,          SEL_SCIF5_1),
        PINMUX_IPSR_MSEL(IP2_27_24,             PWM6_A,         SEL_PWM6_0),
@@ -1043,7 +1046,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP10_27_24,            RIF0_CLK_B,     SEL_DRIF0_1),
        PINMUX_IPSR_MSEL(IP10_27_24,            SCL2_B,         SEL_I2C2_1),
        PINMUX_IPSR_MSEL(IP10_27_24,            TCLK1_A,        SEL_TIMER_TMU_0),
-       PINMUX_IPSR_GPSR(IP10_27_24,            SSI_SCK2_B),
+       PINMUX_IPSR_MSEL(IP10_27_24,            SSI_SCK2_B,     SEL_SSI2_1),
        PINMUX_IPSR_GPSR(IP10_27_24,            TS_SCK0),
 
        PINMUX_IPSR_GPSR(IP10_31_28,            SD0_WP),
@@ -1052,7 +1055,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP10_31_28,            RIF0_D0_B,      SEL_DRIF0_1),
        PINMUX_IPSR_MSEL(IP10_31_28,            SDA2_B,         SEL_I2C2_1),
        PINMUX_IPSR_MSEL(IP10_31_28,            TCLK2_A,        SEL_TIMER_TMU_0),
-       PINMUX_IPSR_GPSR(IP10_31_28,            SSI_WS2_B),
+       PINMUX_IPSR_MSEL(IP10_31_28,            SSI_WS2_B,      SEL_SSI2_1),
        PINMUX_IPSR_GPSR(IP10_31_28,            TS_SDAT0),
 
        /* IPSR11 */
@@ -1070,13 +1073,13 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_MSEL(IP11_11_8,             RX0_A,          SEL_SCIF0_0),
        PINMUX_IPSR_MSEL(IP11_11_8,             HRX1_A,         SEL_HSCIF1_0),
-       PINMUX_IPSR_GPSR(IP11_11_8,             SSI_SCK2_A),
+       PINMUX_IPSR_MSEL(IP11_11_8,             SSI_SCK2_A,     SEL_SSI2_0),
        PINMUX_IPSR_GPSR(IP11_11_8,             RIF1_SYNC),
        PINMUX_IPSR_GPSR(IP11_11_8,             TS_SCK1),
 
        PINMUX_IPSR_MSEL(IP11_15_12,            TX0_A,          SEL_SCIF0_0),
        PINMUX_IPSR_GPSR(IP11_15_12,            HTX1_A),
-       PINMUX_IPSR_GPSR(IP11_15_12,            SSI_WS2_A),
+       PINMUX_IPSR_MSEL(IP11_15_12,            SSI_WS2_A,      SEL_SSI2_0),
        PINMUX_IPSR_GPSR(IP11_15_12,            RIF1_D0),
        PINMUX_IPSR_GPSR(IP11_15_12,            TS_SDAT1),
 
@@ -1181,7 +1184,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP13_19_16,            RIF0_D1_A,      SEL_DRIF0_0),
        PINMUX_IPSR_MSEL(IP13_19_16,            SDA1_B,         SEL_I2C1_1),
        PINMUX_IPSR_MSEL(IP13_19_16,            TCLK2_B,        SEL_TIMER_TMU_1),
-       PINMUX_IPSR_GPSR(IP13_19_16,            SIM0_D_A),
+       PINMUX_IPSR_MSEL(IP13_19_16,            SIM0_D_A,       SEL_SIMCARD_0),
 
        PINMUX_IPSR_GPSR(IP13_23_20,            MLB_DAT),
        PINMUX_IPSR_MSEL(IP13_23_20,            TX0_B,          SEL_SCIF0_1),
@@ -1249,7 +1252,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP15_15_12,            TPU0TO2),
        PINMUX_IPSR_MSEL(IP15_15_12,            SDA1_D,         SEL_I2C1_3),
        PINMUX_IPSR_MSEL(IP15_15_12,            FSO_CFE_1_N_B,  SEL_FSO_1),
-       PINMUX_IPSR_GPSR(IP15_15_12,            SIM0_D_B),
+       PINMUX_IPSR_MSEL(IP15_15_12,            SIM0_D_B,       SEL_SIMCARD_1),
 
        PINMUX_IPSR_GPSR(IP15_19_16,            SSI_SDATA6),
        PINMUX_IPSR_MSEL(IP15_19_16,            HRTS2_N_A,      SEL_HSCIF2_0),
@@ -1534,22 +1537,22 @@ static const unsigned int avb_avtp_pps_mux[] = {
        AVB_AVTP_PPS_MARK,
 };
 
-static const unsigned int avb_avtp_match_a_pins[] = {
-       /* AVB_AVTP_MATCH_A */
+static const unsigned int avb_avtp_match_pins[] = {
+       /* AVB_AVTP_MATCH */
        RCAR_GP_PIN(2, 24),
 };
 
-static const unsigned int avb_avtp_match_a_mux[] = {
-       AVB_AVTP_MATCH_A_MARK,
+static const unsigned int avb_avtp_match_mux[] = {
+       AVB_AVTP_MATCH_MARK,
 };
 
-static const unsigned int avb_avtp_capture_a_pins[] = {
-       /* AVB_AVTP_CAPTURE_A */
+static const unsigned int avb_avtp_capture_pins[] = {
+       /* AVB_AVTP_CAPTURE */
        RCAR_GP_PIN(2, 25),
 };
 
-static const unsigned int avb_avtp_capture_a_mux[] = {
-       AVB_AVTP_CAPTURE_A_MARK,
+static const unsigned int avb_avtp_capture_mux[] = {
+       AVB_AVTP_CAPTURE_MARK,
 };
 
 /* - CAN ------------------------------------------------------------------ */
@@ -3794,8 +3797,8 @@ static const struct {
                SH_PFC_PIN_GROUP(avb_phy_int),
                SH_PFC_PIN_GROUP(avb_mii),
                SH_PFC_PIN_GROUP(avb_avtp_pps),
-               SH_PFC_PIN_GROUP(avb_avtp_match_a),
-               SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+               SH_PFC_PIN_GROUP(avb_avtp_match),
+               SH_PFC_PIN_GROUP(avb_avtp_capture),
                SH_PFC_PIN_GROUP(can0_data),
                SH_PFC_PIN_GROUP(can1_data),
                SH_PFC_PIN_GROUP(can_clk),
@@ -4071,8 +4074,8 @@ static const char * const avb_groups[] = {
        "avb_phy_int",
        "avb_mii",
        "avb_avtp_pps",
-       "avb_avtp_match_a",
-       "avb_avtp_capture_a",
+       "avb_avtp_match",
+       "avb_avtp_capture",
 };
 
 static const char * const can0_groups[] = {
@@ -4967,11 +4970,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL0_1_0 ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-                            GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
-                                  2, 2, 2, 1, 1, 2, 1, 4),
+                            GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
+                                  1, 2, 2, 2, 1, 1, 2, 1, 4),
                             GROUP(
-               /* RESERVED 31, 30 */
-               0, 0, 0, 0,
+               MOD_SEL1_31
+               MOD_SEL1_30
                MOD_SEL1_29
                MOD_SEL1_28
                /* RESERVED 27 */