powerpc/mpc85xx: Add support for single source clocking

Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.

So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock

DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
 normal clocking mode by DDR_Reference clock

-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
 single source clocking mode by DIFF_SYSCLK

Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>

diff --git a/README b/README
index e58e9c0e1c15f3fd26b94ec20247ba9424e30395..a0646c36657b3b69b37a9a1816a27fcdb55d8d43 100644 (file)
--- a/README
+++ b/README
@@ -423,6 +423,11 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
                This value denotes start offset of DSP CCSR space.
 
+               CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+               Single Source Clock is clocking mode present in some of FSL SoC's.
+               In this mode, a single differential clock is used to supply
+               clocks to the sysclock, ddrclock and usbclock.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 7c7467f7bfcb7e8cdff98bbf1c69e56ed9fd80cd..35867dffdd718740184933d86456212e7fc1d09e 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -74,12 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
        uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
        unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
        uint mem_pll_rat;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+       uint single_src;
+#endif
 
        sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+       /*
+        * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
+        * are driven by separate DDR Refclock or single source
+        * differential clock.
+        */
+       single_src = (in_be32(&gur->rcwsr[5]) >>
+                     FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
+                     FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
+       /*
+        * For single source clocking, both ddrclock and syclock
+        * are driven by differential sysclock.
+        */
+       if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
+               printf("Single Source Clock Configuration\n");
+               sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+       } else
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
-       sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+               sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
-       sys_info->freq_ddrbus = sysclk;
+               sys_info->freq_ddrbus = sysclk;
 #endif
 
        sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 244ccbf24fc619f69fb778242b0b952bdd81b56d..3d8bd9a819b0c255d1ffec30a83171075fccf479 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 672e8c6650c39ea703d7cd6307c91b381e92e0b4..68c3c8245338053b473c57923703d6d7859d1ff0 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2        0x00040000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1        0x00020000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2        0x00010000
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK        0x00000011
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK      1
 
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   17