mx6: ddr: Wait before issuing the first MRS cmd

Wait 1ms before issuing the first MRS command to write DDR3 Mode
registers.

There is a requirement to wait a minimum time before issuing command to
the DDR3 device, according to the JEDEC standard this time is 500us
(after RESET_n is de-asserted until CKE becomes active) + tXPR (Reset
CKE Exit time, maximum value 360ns).

It seems that for some reason this is not enforced by the MMDC
controller.

Without this change we experienced random memory initialization failures
with about 2% boot failure rate on specific problematic boards, after
this change we were able to do more than 10.000 power-cycle without a
single failure.

Fixes: fe0f7f7842e1 ("mx6: add mmdc configuration for MX6Q/MX6DL")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>

diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 181df941cfb7a2a117ba51100436e4ff94e78b44..73a637c42d6c6339696eeae16bdc7d06c1bb74b0 100644 (file)
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -1526,6 +1526,11 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
                        ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
 
        /* Step 8: Write Mode Registers to Init DDR3 devices */
+       mdelay(1); /* Wait before issuing the first MRS command.
+                   * Minimum wait time is (tXPR + 500us),
+                   * with max tXPR value 360ns, and 500us wait required after
+                   * RESET_n is de-asserted.
+                   */
        for (cs = 0; cs < sysinfo->ncs; cs++) {
                /* MR2 */
                val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |