arm: socfpga: agilex: Enable Agilex SoC build

Add build support for Agilex SoC.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36c9c2fecd01599e176198879b77f0d07ab532e6..7d159ece1270a60a3daa763e44afb1ec3c7a65f0 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -905,7 +905,7 @@ config ARCH_SOCFPGA
        bool "Altera SOCFPGA family"
        select ARCH_EARLY_INIT_R
        select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
-       select ARM64 if TARGET_SOCFPGA_STRATIX10
+       select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
        select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
        select DM
        select DM_SERIAL
@@ -917,7 +917,7 @@ config ARCH_SOCFPGA
        select SPL_LIBGENERIC_SUPPORT
        select SPL_NAND_SUPPORT if SPL_NAND_DENALI
        select SPL_OF_CONTROL
-       select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
+       select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
        select SPL_SERIAL_SUPPORT
        select SPL_SYSRESET
        select SPL_WATCHDOG_SUPPORT

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 3770e0725857859c1606bccbc836c54e42304426..969698c83fa576fa8a8034aa8d95476049bd3df4 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -29,6 +29,15 @@ config SYS_TEXT_BASE
        default 0x01000040 if TARGET_SOCFPGA_ARRIA10
        default 0x01000040 if TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_AGILEX
+       bool
+       select ARMV8_MULTIENTRY
+       select ARMV8_SET_SMPEN
+       select ARMV8_SPIN_TABLE
+       select CLK
+       select NCORE_CACHE
+       select SPL_CLK if SPL
+
 config TARGET_SOCFPGA_ARRIA5
        bool
        select TARGET_SOCFPGA_GEN5
@@ -75,6 +84,10 @@ choice
        prompt "Altera SOCFPGA board select"
        optional
 
+config TARGET_SOCFPGA_AGILEX_SOCDK
+       bool "Intel SOCFPGA SoCDK (Agilex)"
+       select TARGET_SOCFPGA_AGILEX
+
 config TARGET_SOCFPGA_ARIES_MCVEVK
        bool "Aries MCVEVK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -135,6 +148,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 endchoice
 
 config SYS_BOARD
+       default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -151,6 +165,7 @@ config SYS_BOARD
        default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
+       default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -168,6 +183,7 @@ config SYS_SOC
        default "socfpga"
 
 config SYS_CONFIG_NAME
+       default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 81b6ffc6757abdde3567a59a9f431cb5716e4f69..418f543b20fe850e6d552e76b671bc1e5f9a957f 100644 (file)
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,6 +41,14 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y  += clock_manager_agilex.o
+obj-y  += mailbox_s10.o
+obj-y  += misc_s10.o
+obj-y  += mmu-arm64_s10.o
+obj-y  += reset_manager_s10.o
+obj-y  += system_manager_s10.o
+obj-y  += timer_s10.o
+obj-y  += wrap_pinmux_config_s10.o
+obj-y  += wrap_pll_config_s10.o
 endif
 
 ifdef CONFIG_SPL_BUILD
@@ -59,6 +67,7 @@ obj-y += firewall.o
 obj-y  += spl_s10.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y  += firewall.o
 obj-y  += spl_agilex.o
 endif
 endif

diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
new file mode 100644 (file)
index 0000000..cdb9396
--- /dev/null
+++ b/configs/socfpga_agilex_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set

diff --git a/include/configs/socfpga_agilex_socdk.h b/include/configs/socfpga_agilex_socdk.h
new file mode 100644 (file)
index 0000000..4eede7c
--- /dev/null
+++ b/include/configs/socfpga_agilex_socdk.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_AGILEX_H__
+#define __CONFIG_SOCFGPA_AGILEX_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#endif /* __CONFIG_SOCFGPA_AGILEX_H__ */

diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index f69a55c191edd35bb1cd2c6b238c250f4777aea2..4b274837888c45e717a2d1d9802c3820dbcdf19d 100644 (file)
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -87,7 +87,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
        "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "bootfile=Image\0" \
        "fdt_addr=8000000\0" \
-       "fdtimage=socfpga_stratix10_socdk.dtb\0" \
+       "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
        "mmcroot=/dev/mmcblk0p2\0" \
        "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
                " root=${mmcroot} rw rootwait;" \
@@ -155,10 +155,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 #ifndef __ASSEMBLY__
 unsigned int cm_get_l4_sys_free_clk_hz(void);
 #define CONFIG_DW_WDT_CLOCK_KHZ                (cm_get_l4_sys_free_clk_hz() / 1000)
 #endif
+#else
+#define CONFIG_DW_WDT_CLOCK_KHZ                100000
+#endif
 #endif
 
 /*