global: Migrate CONFIG_SH_ETHER_USE_PORT to CFG

Perform a simple rename of CONFIG_SH_ETHER_USE_PORT to CFG_SH_ETHER_USE_PORT

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 217fbaf55757bbea2fd4205fcb60ccdec7760c69..a9b225e45ecb11388124b50109d6a5b6f67c0b54 100644 (file)
--- a/README
+++ b/README
@@ -541,7 +541,7 @@ The following options need to be configured:
                CONFIG_SH_ETHER
                Support for Renesas on-chip Ethernet controller
 
-                       CONFIG_SH_ETHER_USE_PORT
+                       CFG_SH_ETHER_USE_PORT
                        Define the number of ports to be used
 
                        CFG_SH_ETHER_PHY_ADDR

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 3bf94cb2f7eb568c56ff6cb898442e2e2b2b2414..8f162ca58fbb53cb6c6210e4f955681d41058872 100644 (file)
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -30,8 +30,8 @@
 
 #include "sh_eth.h"
 
-#ifndef CONFIG_SH_ETHER_USE_PORT
-# error "Please define CONFIG_SH_ETHER_USE_PORT"
+#ifndef CFG_SH_ETHER_USE_PORT
+# error "Please define CFG_SH_ETHER_USE_PORT"
 #endif
 #ifndef CFG_SH_ETHER_PHY_ADDR
 # error "Please define CFG_SH_ETHER_PHY_ADDR"
@@ -693,7 +693,7 @@ static int sh_ether_probe(struct udevice *udev)
 
        priv->bus = miiphy_get_dev_by_name(udev->name);
 
-       eth->port = CONFIG_SH_ETHER_USE_PORT;
+       eth->port = CFG_SH_ETHER_USE_PORT;
        eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
        eth->port_info[eth->port].iobase =
                (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);

diff --git a/include/configs/alt.h b/include/configs/alt.h
index 53c31562a5d0b2baebdf32026543b1464fa29d9b..8f03762583e907d904da1ff2cd1c85f855c4b51f 100644 (file)
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -21,7 +21,7 @@
 #define RCAR_GEN2_UBOOT_SDRAM_SIZE     (512 * 1024 * 1024)
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/condor.h b/include/configs/condor.h
index 2c9817cf02c57369d4781d30bfce76e19012618f..50c8d1733838331bd83e885a1dd00fb6af8a9060 100644 (file)
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -14,7 +14,7 @@
 /* Environment compatibility */
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/gose.h b/include/configs/gose.h
index ed7dd70dd964065a1d4cd6dbefdfe90a8828d1f9..7ae0726518da5dcda23a92e0c393b8196d9f727f 100644 (file)
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -20,7 +20,7 @@
 #define RCAR_GEN2_UBOOT_SDRAM_SIZE     (512u * 1024 * 1024)
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 6a11aa61f0fb11de84918d3ef729c027b25fba37..8de4a36e931a310e5b53afedd84e2035673cfd21 100644 (file)
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -17,7 +17,7 @@
 #define CFG_SYS_SDRAM_SIZE             (10 * 1024 * 1024)
 
 /* Network interface */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 31d0795f07fb01d0f59ed1b0906514155539d326..d47d70178ccdba0add012e00878bf35d39602136 100644 (file)
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -20,7 +20,7 @@
 #define RCAR_GEN2_UBOOT_SDRAM_SIZE     (512 * 1024 * 1024)
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/lager.h b/include/configs/lager.h
index 991fc9020ee0fad29a47919ca28daed7b1d4c95e..2577c7a7da671533dca301abd8a9ee8bd6b8001b 100644 (file)
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -21,7 +21,7 @@
 #define RCAR_GEN2_UBOOT_SDRAM_SIZE     (512 * 1024 * 1024)
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/porter.h b/include/configs/porter.h
index 1587c5c5397cc9722fc9bd67a34dcf05adbf056e..2cb430be8b0da573c400ac51cc882789cf9100c9 100644 (file)
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -22,7 +22,7 @@
 #define RCAR_GEN2_UBOOT_SDRAM_SIZE     (1024u * 1024 * 1024)
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/silk.h b/include/configs/silk.h
index 21100c46b1cb2c2525fdfac3ca5a4a86d245705a..7bed32d8553befdfafbe7b4dabdcd402f56c6ad3 100644 (file)
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -22,7 +22,7 @@
 #define RCAR_GEN2_UBOOT_SDRAM_SIZE     (512 * 1024 * 1024)
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK

diff --git a/include/configs/stout.h b/include/configs/stout.h
index 51f4420ed6fae8d83bc3da409d6f74da8d4b0730..1278ba63f4f3dc22331c0b87a146f3319fea7ce1 100644 (file)
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -26,7 +26,7 @@
 #define CFG_SCIF_A
 
 /* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT       0
+#define CFG_SH_ETHER_USE_PORT  0
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
 #define CFG_SH_ETHER_CACHE_WRITEBACK