zynq: Update CLK in bdinfo

ARM has specific clk entries which should be also setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c
index 43071111c4dc8c45f0daee59d39e26f49a406b84..d2885dc2b9e3e9d6444684ed103b1e1962b2b929 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/clk.c
+++ b/arch/arm/cpu/armv7/zynq/clk.c
@@ -161,6 +161,8 @@ static void init_ddr_clocks(void)
        clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
                        DIV_ROUND_CLOSEST(prate, div0), div1);
        clks[dci_clk].name = "dci";
+
+       gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
 }
 
 static void init_cpu_clocks(void)
@@ -593,6 +595,9 @@ int set_cpu_clk_info(void)
        init_periph_clocks();
        init_aper_clocks();
 
+       gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+       gd->bd->bi_dsp_freq = 0;
+
        return 0;
 }