OMAP5-uevm: USB: Add xHCI host contoller support

Add the call back into the board file for to enable
the SMPS10 VBUS regulator.

Signed-off-by: Dan Murphy <dmurphy@ti.com>

diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 47063309e5698020864e641d4bf1b6eeb071e4b3..5fc3473ecc2d2339a572ff98945181af4c84a936 100644 (file)
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -14,7 +14,7 @@
 
 #include "mux_data.h"
 
-#ifdef CONFIG_USB_EHCI
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
 #include <usb.h>
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
@@ -72,6 +72,35 @@ int board_eth_init(bd_t *bis)
        return 0;
 }
 
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+static void enable_host_clocks(void)
+{
+       int auxclk;
+       int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+                               OPTFCLKEN_HSIC480M_P3_CLK |
+                               OPTFCLKEN_HSIC60M_P2_CLK |
+                               OPTFCLKEN_HSIC480M_P2_CLK |
+                               OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+       /* Enable port 2 and 3 clocks*/
+       setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+       /* Enable port 2 and 3 usb host ports tll clocks*/
+       setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+                       (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+#ifdef CONFIG_USB_XHCI_OMAP
+       /* Enable the USB OTG Super speed clocks */
+       setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+                       (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
+#endif
+
+       auxclk = readl((*prcm)->scrm_auxclk1);
+       /* Request auxilary clock */
+       auxclk |= AUXCLK_ENABLE_MASK;
+       writel(auxclk, (*prcm)->scrm_auxclk1);
+}
+#endif
+
 /**
  * @brief misc_init_r - Configure EVM board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
@@ -84,6 +113,7 @@ int misc_init_r(void)
 #ifdef CONFIG_PALMAS_POWER
        palmas_init_settings();
 #endif
+
        return 0;
 }
 
@@ -129,26 +159,9 @@ static struct omap_usbhs_board_data usbhs_bdata = {
        .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
 };
 
-static void enable_host_clocks(void)
-{
-       int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
-                               OPTFCLKEN_HSIC480M_P3_CLK |
-                               OPTFCLKEN_HSIC60M_P2_CLK |
-                               OPTFCLKEN_HSIC480M_P2_CLK |
-                               OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
-       /* Enable port 2 and 3 clocks*/
-       setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
-       /* Enable port 2 and 3 usb host ports tll clocks*/
-       setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
-                       (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
-}
-
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        int ret;
-       int auxclk;
        int reg;
        uint8_t device_mac[6];
 
@@ -171,11 +184,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
                eth_setenv_enetaddr("usbethaddr", device_mac);
        }
 
-       auxclk = readl((*prcm)->scrm_auxclk1);
-       /* Request auxilary clock */
-       auxclk |= AUXCLK_ENABLE_MASK;
-       writel(auxclk, (*prcm)->scrm_auxclk1);
-
        ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
        if (ret < 0) {
                puts("Failed to initialize ehci\n");
@@ -203,3 +211,23 @@ void usb_hub_reset_devices(int port)
        }
 }
 #endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+/**
+ * @brief board_usb_init - Configure EVM board specific configurations
+ * for the LDO's and clocks for the USB blocks.
+ *
+ * @return 0
+ */
+int board_usb_init(void)
+{
+       int ret;
+#ifdef CONFIG_PALMAS_USB_SS_PWR
+       ret = palmas_enable_ss_ldo();
+#endif
+
+       enable_host_clocks();
+
+       return 0;
+}
+#endif