xes: Use common PCI initialization code

Common Freescale code for PCI initialization now exists, so migrate X-ES
boards to use it.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index ece7882577852c5faca67d0a453226e99ddcd3c6..f425ceedc45664f90b48e13b3f84b3adb12f6429 100644 (file)
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -25,10 +25,10 @@
 #include <pci.h>
 #include <asm/fsl_pci.h>
 #include <asm/io.h>
+#include <linux/compiler.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
-int first_free_busno = 0;
 
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
@@ -43,111 +43,6 @@ static struct pci_controller pcie2_hose;
 static struct pci_controller pcie3_hose;
 #endif
 
-#ifdef CONFIG_MPC8572
-/* Correlate host/agent POR bits to usable info. Table 4-14 */
-struct host_agent_cfg_t {
-       uchar pcie_root[3];
-       uchar rio_host;
-} host_agent_cfg[8] = {
-       {{0, 0, 0}, 0},
-       {{0, 1, 1}, 1},
-       {{1, 0, 1}, 0},
-       {{1, 1, 0}, 1},
-       {{0, 0, 1}, 0},
-       {{0, 1, 0}, 1},
-       {{1, 0, 0}, 0},
-       {{1, 1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-15 */
-struct io_port_cfg_t {
-       uchar pcie_width[3];
-       uchar rio_width;
-} io_port_cfg[16] = {
-       {{0, 0, 0}, 0},
-       {{0, 0, 0}, 0},
-       {{4, 0, 0}, 0},
-       {{4, 4, 0}, 0},
-       {{0, 0, 0}, 0},
-       {{0, 0, 0}, 0},
-       {{0, 0, 0}, 4},
-       {{4, 2, 2}, 0},
-       {{0, 0, 0}, 0},
-       {{0, 0, 0}, 0},
-       {{0, 0, 0}, 0},
-       {{4, 0, 0}, 4},
-       {{4, 0, 0}, 4},
-       {{0, 0, 0}, 4},
-       {{0, 0, 0}, 4},
-       {{8, 0, 0}, 0},
-};
-#elif defined CONFIG_MPC8548
-/* Correlate host/agent POR bits to usable info. Table 4-12 */
-struct host_agent_cfg_t {
-       uchar pci_host[2];
-       uchar pcie_root[1];
-       uchar rio_host;
-} host_agent_cfg[8] = {
-       {{1, 1}, {0}, 0},
-       {{1, 1}, {1}, 0},
-       {{1, 1}, {0}, 1},
-       {{0, 0}, {0}, 0}, /* reserved */
-       {{0, 1}, {1}, 0},
-       {{1, 1}, {1}, 0},
-       {{0, 1}, {1}, 1},
-       {{1, 1}, {1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-13 */
-struct io_port_cfg_t {
-       uchar pcie_width[1];
-       uchar rio_width;
-} io_port_cfg[8] = {
-       {{0}, 0},
-       {{0}, 0},
-       {{0}, 0},
-       {{4}, 4},
-       {{4}, 4},
-       {{0}, 4},
-       {{0}, 4},
-       {{8}, 0},
-};
-#elif defined CONFIG_MPC86xx
-/* Correlate host/agent POR bits to usable info. Table 4-17 */
-struct host_agent_cfg_t {
-       uchar pcie_root[2];
-       uchar rio_host;
-} host_agent_cfg[8] = {
-       {{0, 0}, 0},
-       {{1, 0}, 1},
-       {{0, 1}, 0},
-       {{1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-16 */
-struct io_port_cfg_t {
-       uchar pcie_width[2];
-       uchar rio_width;
-} io_port_cfg[16] = {
-       {{0, 0}, 0},
-       {{0, 0}, 0},
-       {{8, 0}, 0},
-       {{8, 8}, 0},
-       {{0, 0}, 0},
-       {{8, 0}, 4},
-       {{8, 0}, 4},
-       {{8, 0}, 4},
-       {{0, 0}, 0},
-       {{0, 0}, 4},
-       {{0, 0}, 4},
-       {{0, 0}, 4},
-       {{0, 0}, 0},
-       {{0, 0}, 0},
-       {{0, 8}, 0},
-       {{8, 8}, 0},
-};
-#endif
-
 /*
  * 85xx and 86xx share naming conventions, but different layout.
  * Correlate names to CPU-specific values to share common
@@ -173,22 +68,22 @@ struct io_port_cfg_t {
 
 void pci_init_board(void)
 {
-       struct pci_controller *hose;
-       volatile ccsr_fsl_pci_t *pci;
-       int width;
-       int host;
+       struct fsl_pci_info pci_info[3];
+       int first_free_busno = 0;
+       int num = 0;
+       int pcie_ep;
+       __maybe_unused int pcie_configured;
+
 #if defined(CONFIG_MPC85xx)
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #elif defined(CONFIG_MPC86xx)
        immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
        volatile ccsr_gur_t *gur = &immap->im_gur;
 #endif
-       uint devdisr = in_be32(&gur->devdisr);
-       uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >>
+       u32 devdisr = in_be32(&gur->devdisr);
+       u32 pordevsr = in_be32(&gur->pordevsr);
+       __maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
                        MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
-       uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >>
-                       MPC8xxx_PORBMSR_HA_SHIFT;
-       struct pci_region *r;
 
 #ifdef CONFIG_PCI1
        uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
@@ -197,49 +92,19 @@ void pci_init_board(void)
        uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
        uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 
-       width = 0; /* Silence compiler warning... */
-       io_sel &= 0xf; /* Silence compiler warning... */
-       pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-       hose = &pci1_hose;
-       host = host_agent_cfg[host_agent].pci_host[0];
-       r = hose->regions;
-
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+               SET_STD_PCI_INFO(pci_info[num], 1);
+               pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
                printf("\n    PCI1: %d bit %s, %s %d MHz, %s, %s\n",
                        pci_32 ? 32 : 64,
                        pcix ? "PCIX" : "PCI",
                        pci_spd_norm ? ">=" : "<=",
                        pcix ? freq * 2 : freq,
-                       host ? "host" : "agent",
+                       pcie_ep ? "agent" : "host",
                        pci_arb ? "arbiter" : "external-arbiter");
 
-               /* outbound memory */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCI1_MEM_BASE,
-                               CONFIG_SYS_PCI1_MEM_PHYS,
-                               CONFIG_SYS_PCI1_MEM_SIZE,
-                               PCI_REGION_MEM);
-
-               /* outbound io */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCI1_IO_BASE,
-                               CONFIG_SYS_PCI1_IO_PHYS,
-                               CONFIG_SYS_PCI1_IO_SIZE,
-                               PCI_REGION_IO);
-
-               hose->region_count = r - hose->regions;
-
-               hose->first_busno = first_free_busno;
-
-               fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-               /* Unlock inbound PCI configuration cycles */
-               if (!host)
-                       fsl_pci_config_unlock(hose);
-
-               first_free_busno = hose->last_busno + 1;
-               printf("    PCI1 on bus %02x - %02x\n",
-                       hose->first_busno, hose->last_busno);
+               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+                                       &pci1_hose, first_free_busno);
        } else {
                printf("    PCI1: disabled\n");
        }
@@ -247,148 +112,53 @@ void pci_init_board(void)
        /* PCI1 not present on MPC8572 */
        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
-#ifdef CONFIG_PCIE1
-       pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-       hose = &pcie1_hose;
-       host = host_agent_cfg[host_agent].pcie_root[0];
-       width = io_port_cfg[io_sel].pcie_width[0];
-       r = hose->regions;
-
-       if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
-               printf("\n    PCIE1 connected as %s (x%d)",
-                       host ? "Root Complex" : "Endpoint", width);
-               if (in_be32(&pci->pme_msg_det)) {
-                       out_be32(&pci->pme_msg_det, 0xffffffff);
-                       debug(" with errors.  Clearing.  Now 0x%08x",
-                               in_be32(&pci->pme_msg_det));
-               }
-               printf("\n");
-
-               /* outbound memory */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCIE1_MEM_BASE,
-                               CONFIG_SYS_PCIE1_MEM_PHYS,
-                               CONFIG_SYS_PCIE1_MEM_SIZE,
-                               PCI_REGION_MEM);
-
-               /* outbound io */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCIE1_IO_BASE,
-                               CONFIG_SYS_PCIE1_IO_PHYS,
-                               CONFIG_SYS_PCIE1_IO_SIZE,
-                               PCI_REGION_IO);
-
-               hose->region_count = r - hose->regions;
-
-               hose->first_busno = first_free_busno;
-
-               fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 
-               /* Unlock inbound PCI configuration cycles */
-               if (!host)
-                       fsl_pci_config_unlock(hose);
-
-               first_free_busno = hose->last_busno + 1;
-               printf("    PCIE1 on bus %02x - %02x\n",
-                               hose->first_busno, hose->last_busno);
+#ifdef CONFIG_PCIE1
+       pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+       if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
+               SET_STD_PCIE_INFO(pci_info[num], 1);
+               pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+               printf("    PCIE1 connected as %s\n",
+                       pcie_ep ? "Endpoint" : "Root Complex");
+               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+                                       &pcie1_hose, first_free_busno);
+       } else {
+               printf("    PCIE1: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
 #endif /* CONFIG_PCIE1 */
 
 #ifdef CONFIG_PCIE2
-       pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-       hose = &pcie2_hose;
-       host = host_agent_cfg[host_agent].pcie_root[1];
-       width = io_port_cfg[io_sel].pcie_width[1];
-       r = hose->regions;
-
-       if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
-               printf("\n    PCIE2 connected as %s (x%d)",
-                       host ? "Root Complex" : "Endpoint", width);
-               if (in_be32(&pci->pme_msg_det)) {
-                       out_be32(&pci->pme_msg_det, 0xffffffff);
-                       debug(" with errors.  Clearing.  Now 0x%08x",
-                               in_be32(&pci->pme_msg_det));
-               }
-               printf("\n");
-
-               /* outbound memory */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCIE2_MEM_BASE,
-                               CONFIG_SYS_PCIE2_MEM_PHYS,
-                               CONFIG_SYS_PCIE2_MEM_SIZE,
-                               PCI_REGION_MEM);
-
-               /* outbound io */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCIE2_IO_BASE,
-                               CONFIG_SYS_PCIE2_IO_PHYS,
-                               CONFIG_SYS_PCIE2_IO_SIZE,
-                               PCI_REGION_IO);
-
-               hose->region_count = r - hose->regions;
-
-               hose->first_busno = first_free_busno;
-
-               fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-               /* Unlock inbound PCI configuration cycles */
-               if (!host)
-                       fsl_pci_config_unlock(hose);
-
-               first_free_busno = hose->last_busno + 1;
-               printf("    PCIE2 on bus %02x - %02x\n",
-                               hose->first_busno, hose->last_busno);
+       pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+       if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
+               SET_STD_PCIE_INFO(pci_info[num], 2);
+               pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+               printf("    PCIE2 connected as %s\n",
+                       pcie_ep ? "Endpoint" : "Root Complex");
+               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+                                       &pcie2_hose, first_free_busno);
+       } else {
+               printf("    PCIE2: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
 #endif /* CONFIG_PCIE2 */
 
 #ifdef CONFIG_PCIE3
-       pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
-       hose = &pcie3_hose;
-       host = host_agent_cfg[host_agent].pcie_root[2];
-       width = io_port_cfg[io_sel].pcie_width[2];
-       r = hose->regions;
-
-       if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
-               printf("\n    PCIE3 connected as %s (x%d)",
-                       host ? "Root Complex" : "Endpoint", width);
-               if (in_be32(&pci->pme_msg_det)) {
-                       out_be32(&pci->pme_msg_det, 0xffffffff);
-                       debug(" with errors.  Clearing.  Now 0x%08x",
-                               in_be32(&pci->pme_msg_det));
-               }
-               printf("\n");
-
-               /* outbound memory */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCIE3_MEM_BASE,
-                               CONFIG_SYS_PCIE3_MEM_PHYS,
-                               CONFIG_SYS_PCIE3_MEM_SIZE,
-                               PCI_REGION_MEM);
-
-               /* outbound io */
-               pci_set_region(r++,
-                               CONFIG_SYS_PCIE3_IO_BASE,
-                               CONFIG_SYS_PCIE3_IO_PHYS,
-                               CONFIG_SYS_PCIE3_IO_SIZE,
-                               PCI_REGION_IO);
-
-               hose->region_count = r - hose->regions;
-
-               hose->first_busno = first_free_busno;
-
-               fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-               /* Unlock inbound PCI configuration cycles */
-               if (!host)
-                       fsl_pci_config_unlock(hose);
-
-               first_free_busno = hose->last_busno + 1;
-               printf("    PCIE3 on bus %02x - %02x\n",
-                               hose->first_busno, hose->last_busno);
+       pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+
+       if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
+               SET_STD_PCIE_INFO(pci_info[num], 3);
+               pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+               printf("    PCIE3 connected as %s\n",
+                       pcie_ep ? "Endpoint" : "Root Complex");
+               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+                                       &pcie3_hose, first_free_busno);
+       } else {
+               printf("    PCIE3: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);

diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 1851997916c07970220e02fc6bdef759ade87b00..9ff28a2913264040543c7894d209627d46e0d3c2 100644 (file)
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -324,18 +324,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* PCIE1 - PEX8518 */
-#define CONFIG_SYS_PCIE1_MEM_BASE      0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x40000000      /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
 
 /* PCIE2 - VPX P1 */
-#define CONFIG_SYS_PCIE2_MEM_BASE      0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000      /* 8M */
 

diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index d0e9492b4ed73a1b7884ac5e834737a7842e4ecf..db03777a79dcbf183c3895b514843903d0b67d60 100644 (file)
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -268,10 +268,10 @@
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS                0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x40000000      /* 1G */
-#define CONFIG_SYS_PCI1_IO_BASE                0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS         0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS                0xe8000000
 #define CONFIG_SYS_PCI1_IO_SIZE                0x00800000      /* 1M */
 

diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 629dc0d89c6e2c77c94e891f7890b7316d4c9b35..01047c85eee18fc6bdcc7a8113dd9b2fdd9d5c55 100644 (file)
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -334,18 +334,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* PCIE1 - VPX P1 */
-#define CONFIG_SYS_PCIE1_MEM_BASE      0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x40000000      /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
 
 /* PCIE2 - PEX8518 */
-#define CONFIG_SYS_PCIE2_MEM_BASE      0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000      /* 8M */