arm: mach-k3: j721s2_init: Support less than max DDR controllers

The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>

diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index fb0708bae162a4206b3d6c77205089f0875c7b90..3374889558abadfb5e1d01c811004d7b2355edea 100644 (file)
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -228,7 +228,7 @@ void k3_mem_init(void)
                        panic("DRAM 0 init failed: %d\n", ret);
 
                ret = uclass_next_device_err(&dev);
-               if (ret)
+               if (ret && ret != -ENODEV)
                        panic("DRAM 1 init failed: %d\n", ret);
        }
        spl_enable_cache();