tegra: add addresses of SPI SLINK controllers

Add I/O addresses of SPI SLINK controllers 1-6

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 013a3c5ce2013e498804581d696aca8f98556321..5273fa1125c64d789439138f3a2472e8b12fb65b 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -40,6 +40,12 @@
 #define NV_PA_APB_UARTE_BASE   (NV_PA_APB_MISC_BASE + 0x6400)
 #define NV_PA_NAND_BASE                (NV_PA_APB_MISC_BASE + 0x8000)
 #define NV_PA_SPI_BASE         (NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_SLINK1_BASE      (NV_PA_APB_MISC_BASE + 0xD400)
+#define NV_PA_SLINK2_BASE      (NV_PA_APB_MISC_BASE + 0xD600)
+#define NV_PA_SLINK3_BASE      (NV_PA_APB_MISC_BASE + 0xD800)
+#define NV_PA_SLINK4_BASE      (NV_PA_APB_MISC_BASE + 0xDA00)
+#define NV_PA_SLINK5_BASE      (NV_PA_APB_MISC_BASE + 0xDC00)
+#define NV_PA_SLINK6_BASE      (NV_PA_APB_MISC_BASE + 0xDE00)
 #define TEGRA_DVC_BASE         (NV_PA_APB_MISC_BASE + 0xD000)
 #define NV_PA_PMC_BASE         (NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE         (NV_PA_APB_MISC_BASE + 0xF400)