CONFIG_PHYLIB=y
CONFIG_PHY_FIXED=y
CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Ethernet */
-#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_FIXED_SPEED _1000BASET
#define CONFIG_ARP_TIMEOUT 1500UL
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#endif
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
-#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
-
-#define CONFIG_PHYLIB
#endif
#define CONFIG_MFG_ENV_SETTINGS \
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define QSGMII2_PORT4_PHY_ADDR 0x1f
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
-#define CONFIG_PHY_GIGE
#endif
#endif
/* MAC/PHY configuration */
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
#endif
/* MAC/PHY configuration */
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#endif
/* MAC/PHY configuration */
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
#endif
#ifdef CONFIG_CMD_NET
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_BOARD_SIZE_LIMIT 715776
/* Ethernet Configuration */
-#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 1
#define FEC_QUIRK_ENET_MAC
-#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
#endif
/* Initial environment variables */