mmc: dwmmc: only clear handled interrupts

Unconditionally clearing DTO when RXDR is set leads to spurious timeouts
in FIFO mode transfers if events occur in the following order:

	mask = dwmci_readl(host, DWMCI_RINTSTS);

	// Hardware asserts DWMCI_INTMSK_DTO here

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO);

	if (mask & DWMCI_INTMSK_DTO) {
		// Unreachable as DTO is cleared without being handled!
		return 0;
	}

Only clear interrupts that we have seen and are handling so that DTO is
not missed.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Rock PI 4B)
Tested-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 4232c5eb8c31681e383dfddf3da7f3e4a6ce8e8e..5085a3b491dac771fc931d171119626a20112a46 100644 (file)
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -168,7 +168,8 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
                        if (data->flags == MMC_DATA_READ &&
                            (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) {
                                dwmci_writel(host, DWMCI_RINTSTS,
-                                            DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO);
+                                            mask & (DWMCI_INTMSK_RXDR |
+                                                    DWMCI_INTMSK_DTO));
                                while (size) {
                                        ret = dwmci_fifo_ready(host,
                                                        DWMCI_FIFO_EMPTY,