]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
rockchip: rk3588: Sync device tree with linux v6.7
authorJonas Karlman <jonas@kwiboo.se>
Fri, 26 Jan 2024 22:14:52 +0000 (22:14 +0000)
committerKever Yang <kever.yang@rock-chips.com>
Sun, 4 Feb 2024 10:47:25 +0000 (18:47 +0800)
Sync rk3588 device tree from linux v6.7.

Also drop the rockchip,rk3568-dwc3 compatible now that dwc3-generic
driver support the rockchip,rk3588-dwc3 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
arch/arm/dts/rk3588-turing-rk1.dtsi
arch/arm/dts/rk3588-u-boot.dtsi
arch/arm/dts/rk3588s-orangepi-5.dts
arch/arm/dts/rk3588s-pinctrl.dtsi
arch/arm/dts/rk3588s-u-boot.dtsi
arch/arm/dts/rk3588s.dtsi
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c

index 9570b34aca2e9308b63fb49bd44af8415454b515..d88c0e852356518a95f9dd9d8bb1c5bccd999384 100644 (file)
 &pinctrl {
        fan {
                fan_int: fan-int {
-                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
        hym8563 {
                hym8563_int: hym8563-int {
-                       rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+                       rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
                };
        };
 
index 31046fc7febbf059233562cfb0d0adb89b883067..992f7b5d66378627cb5976d2fb4fd69198692f4d 100644 (file)
@@ -7,7 +7,7 @@
 
 / {
        usb_host1_xhci: usb@fc400000 {
-               compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
+               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
                reg = <0x0 0xfc400000 0x0 0x400000>;
                interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
index 8f399c4317bdadb54540b2099d1e869fa94d979d..e3a839a12dc6f07bb4247fc30bb2af18b15d4ac2 100644 (file)
@@ -38,7 +38,7 @@
        leds {
                compatible = "gpio-leds";
                pinctrl-names = "default";
-               pinctrl-0 =<&leds_gpio>;
+               pinctrl-0 = <&leds_gpio>;
 
                led-1 {
                        gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
index 63151d9d237755f4c471e96e18dd90e09675de47..30db12c4fc82b54ca90eefafa4720bda57e0f9e4 100644 (file)
                emmc_data_strobe: emmc-data-strobe {
                        rockchip,pins =
                                /* emmc_data_strobe */
-                               <2 RK_PA2 1 &pcfg_pull_none>;
+                               <2 RK_PA2 1 &pcfg_pull_down>;
                };
        };
 
index c0fd16c4022b93102d833f79f2619a8b86f6d37b..ebee2131ceeb22d564655c0b0987ec0238b5539b 100644 (file)
@@ -22,7 +22,7 @@
        };
 
        usb_host0_xhci: usb@fc000000 {
-               compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
+               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
                reg = <0x0 0xfc000000 0x0 0x400000>;
                interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
                status = "disabled";
        };
 
-       usb_host2_xhci: usb@fcd00000 {
-               compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
-               reg = <0x0 0xfcd00000 0x0 0x400000>;
-               interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
-               clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
-                        <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
-                        <&cru CLK_PIPEPHY2_PIPE_U3_G>;
-               clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
-               dr_mode = "host";
-               phys = <&combphy2_psu PHY_TYPE_USB3>;
-               phy-names = "usb3-phy";
-               phy_type = "utmi_wide";
-               resets = <&cru SRST_A_USB3OTG2>;
-               snps,dis_enblslpm_quirk;
-               snps,dis-u2-freeclk-exists-quirk;
-               snps,dis-del-phy-power-chg-quirk;
-               snps,dis-tx-ipgap-linecheck-quirk;
-               snps,dis_rxdet_inp3_quirk;
-               status = "disabled";
-       };
-
-       pmu1_grf: syscon@fd58a000 {
-               bootph-all;
-               compatible = "rockchip,rk3588-pmu1-grf", "syscon";
-               reg = <0x0 0xfd58a000 0x0 0x2000>;
-       };
-
        usbdpphy0_grf: syscon@fd5c8000 {
                compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
                reg = <0x0 0xfd5c8000 0x0 0x4000>;
        status = "okay";
 };
 
+&pmu1grf {
+       bootph-all;
+};
+
 &scmi {
        bootph-pre-ram;
 };
index 61a9a11c3bb0e46640d258f10973937ed83feb0e..8aa0499f9b032d3a2da92d416421e56df15e9f06 100644 (file)
                status = "disabled";
        };
 
+       usb_host2_xhci: usb@fcd00000 {
+               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+               reg = <0x0 0xfcd00000 0x0 0x400000>;
+               interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
+                        <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
+                        <&cru CLK_PIPEPHY2_PIPE_U3_G>;
+               clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
+               dr_mode = "host";
+               phys = <&combphy2_psu PHY_TYPE_USB3>;
+               phy-names = "usb3-phy";
+               phy_type = "utmi_wide";
+               resets = <&cru SRST_A_USB3OTG2>;
+               snps,dis_enblslpm_quirk;
+               snps,dis-u2-freeclk-exists-quirk;
+               snps,dis-del-phy-power-chg-quirk;
+               snps,dis-tx-ipgap-linecheck-quirk;
+               snps,dis_rxdet_inp3_quirk;
+               status = "disabled";
+       };
+
+       pmu1grf: syscon@fd58a000 {
+               compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
+               reg = <0x0 0xfd58a000 0x0 0x10000>;
+       };
+
        sys_grf: syscon@fd58c000 {
                compatible = "rockchip,rk3588-sys-grf", "syscon";
                reg = <0x0 0xfd58c000 0x0 0x1000>;
                };
        };
 
+       dfi: dfi@fe060000 {
+               reg = <0x00 0xfe060000 0x00 0x10000>;
+               compatible = "rockchip,rk3588-dfi";
+               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
+               rockchip,pmu = <&pmu1grf>;
+       };
+
        gmac1: ethernet@fe1c0000 {
                compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
                reg = <0x0 0xfe1c0000 0x0 0x10000>;
index e8772d3a38247966711b34c0267caf12fa5a0ad5..7b2cf37d9da1e36f435a050a8e614047ca4b038d 100644 (file)
@@ -10,7 +10,7 @@
 
 static const struct udevice_id rk3588_syscon_ids[] = {
        { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
-       { .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
+       { .compatible = "rockchip,rk3588-pmugrf",  .data = ROCKCHIP_SYSCON_PMUGRF },
        { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF },
        { .compatible = "rockchip,rk3588-vo-grf",  .data = ROCKCHIP_SYSCON_VO_GRF },
        { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },