]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level
authorQuentin Schulz <quentin.schulz@cherry.de>
Thu, 23 May 2024 16:59:34 +0000 (18:59 +0200)
committerKever Yang <kever.yang@rock-chips.com>
Fri, 24 May 2024 09:58:59 +0000 (17:58 +0800)
This is the kind of setting that typically doesn't need to be changed
between boards based on the same SoC, so let's make it the default in
PX30 Kconfig so we don't have to care about it in the defconfig if we
don't want to.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
arch/arm/mach-rockchip/px30/Kconfig
configs/evb-px30_defconfig
configs/firefly-px30_defconfig
configs/odroid-go2_defconfig
configs/px30-core-ctouch2-of10-px30_defconfig
configs/px30-core-ctouch2-px30_defconfig
configs/px30-core-edimm2.2-px30_defconfig
configs/ringneck-px30_defconfig

index 23f8f430c4aea9cae211b27e9dc72cc94acbc827..e39472604c3a88bfc5b8d9c1faa15ea937624897 100644 (file)
@@ -83,6 +83,9 @@ config TPL_TEXT_BASE
 config TPL_STACK
        default 0xff0e4fff
 
+config TPL_SYS_MALLOC_F_LEN
+       default 0x600
+
 config DEBUG_UART_CHANNEL
        int "Mux channel to use for debug UART2/UART3"
        depends on DEBUG_UART_BOARD_INIT
index 07c56a45ec0ff82b72a22c4fe8c16f00848f023f..73a3c6120e067d01404dd0bd3b514af9d16258e4 100644 (file)
@@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_EVB_PX30=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
index e5377dcdf3dbc7296234e66de3f591efba9f676b..0a14b3936676d2f9e35ecf7d81077cdb3c2331a5 100644 (file)
@@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
index 99d7149a44ca3efe6841b42c923019ed2015abbe..3c1abb83ed95690a049317ef296f20d4191edd7e 100644 (file)
@@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
index a2801ec7796763d557a2af67713f4151b3e1d522..87a39e115df8cc518f455293c583ad2728314c46 100644 (file)
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
index cc33e275742353ce25f3db01346c3d0b033e10b6..7162c117beba14749412d19fe0a1203d2aa7dbd7 100644 (file)
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
index 99e1b2fc7ae4b450d191c80abc6fb073c7e9d669..1182f60358f86f1e4cec7136f45ce3b474f124d2 100644 (file)
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
index 67a44eda6845ef54598edc11e050129ed6f23129..0df1b8a59ac1821d243be0878b988927f871dc35 100644 (file)
@@ -17,7 +17,6 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_RINGNECK_PX30=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y