#define sunxi_nand_lookup_timing(l, p, c) \
_sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
-static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
+static int sunxi_nand_chip_set_timings(struct sunxi_nfc *nfc,
+ struct sunxi_nand_chip *chip,
const struct nand_sdr_timings *timings)
{
u32 min_clk_period = 0;
return 0;
}
-static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
+static int sunxi_nand_chip_init_timings(struct sunxi_nfc *nfc,
+ struct sunxi_nand_chip *chip)
{
struct mtd_info *mtd = nand_to_mtd(&chip->nand);
const struct nand_sdr_timings *timings;
if (IS_ERR(timings))
return PTR_ERR(timings);
- return sunxi_nand_chip_set_timings(chip, timings);
+ return sunxi_nand_chip_set_timings(nfc, chip, timings);
}
static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
}
if (i >= ARRAY_SIZE(strengths)) {
- dev_err(nfc->dev, "unsupported strength\n");
+ dev_err(mtd->dev, "unsupported strength\n");
ret = -ENOTSUPP;
goto err;
}
nsels /= sizeof(u32);
if (!nsels || nsels > 8) {
- dev_err(dev, "invalid reg property size\n");
+ dev_err(nfc->dev, "invalid reg property size\n");
return -EINVAL;
}
(nsels * sizeof(struct sunxi_nand_chip_sel)),
GFP_KERNEL);
if (!chip) {
- dev_err(dev, "could not allocate chip\n");
+ dev_err(nfc->dev, "could not allocate chip\n");
return -ENOMEM;
}
ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
if (ret) {
- dev_err(dev, "could not retrieve reg property: %d\n", ret);
+ dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
return ret;
}
ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
nsels);
if (ret) {
- dev_err(dev, "could not retrieve reg property: %d\n", ret);
+ dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
return ret;
}
int tmp = cs[i];
if (tmp > NFC_MAX_CS) {
- dev_err(dev,
- "invalid reg value: %u (max CS = 7)\n",
- tmp);
+ dev_err(nfc->dev,
+ "invalid reg value: %u (max CS = 7)\n", tmp);
return -EINVAL;
}
if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
- dev_err(dev, "CS %d already assigned\n", tmp);
+ dev_err(nfc->dev, "CS %d already assigned\n", tmp);
return -EINVAL;
}
timings = onfi_async_timing_mode_to_sdr_timings(0);
if (IS_ERR(timings)) {
ret = PTR_ERR(timings);
- dev_err(dev,
+ dev_err(nfc->dev,
"could not retrieve timings for ONFI mode 0: %d\n",
ret);
return ret;
}
- ret = sunxi_nand_chip_set_timings(chip, timings);
+ ret = sunxi_nand_chip_set_timings(nfc, chip, timings);
if (ret) {
- dev_err(dev, "could not configure chip timings: %d\n", ret);
+ dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
return ret;
}
nand->options |= NAND_SUBPAGE_READ;
- ret = sunxi_nand_chip_init_timings(chip);
+ ret = sunxi_nand_chip_init_timings(nfc, chip);
if (ret) {
- dev_err(dev, "could not configure chip timings: %d\n", ret);
+ dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
return ret;
}
ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
if (ret) {
- dev_err(dev, "ECC init failed: %d\n", ret);
+ dev_err(nfc->dev, "ECC init failed: %d\n", ret);
return ret;
}
ret = nand_scan_tail(mtd);
if (ret) {
- dev_err(dev, "nand_scan_tail failed: %d\n", ret);
+ dev_err(nfc->dev, "nand_scan_tail failed: %d\n", ret);
return ret;
}
ret = nand_register(devnum, mtd);
if (ret) {
- dev_err(dev, "failed to register mtd device: %d\n", ret);
+ dev_err(nfc->dev, "failed to register mtd device: %d\n", ret);
return ret;
}
i++;
if (i > 8) {
- dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
+ dev_err(nfc->dev, "too many NAND chips: %d (max = 8)\n", i);
return -EINVAL;
}
ret = sunxi_nand_chips_init(node, nfc);
if (ret) {
- dev_err(dev, "failed to init nand chips\n");
+ dev_err(nfc->dev, "failed to init nand chips\n");
goto err;
}