]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: keystone2: Remove unsed external clocks
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 28 Jul 2015 08:46:47 +0000 (14:16 +0530)
committerTom Rini <trini@konsulko.com>
Thu, 13 Aug 2015 00:47:54 +0000 (20:47 -0400)
Remove unused external clocks and make a common definition
for all keystone platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/mach-keystone/clock-k2e.c
arch/arm/mach-keystone/clock-k2l.c
arch/arm/mach-keystone/include/mach/clock-k2e.h
arch/arm/mach-keystone/include/mach/clock-k2hk.h
arch/arm/mach-keystone/include/mach/clock-k2l.h
arch/arm/mach-keystone/include/mach/clock.h
board/ti/ks2_evm/board_k2e.c
board/ti/ks2_evm/board_k2hk.c
board/ti/ks2_evm/board_k2l.c

index b23d2a561edd9c60b6d8ae9f235109c04ed3eb30..7d163a4b1ab99c193f82236ff1faafd850d4d7fe 100644 (file)
@@ -43,7 +43,7 @@ static unsigned long pll_freq_get(int pll)
                        reg = KS2_PASSPLLCTL0;
                        break;
                case DDR3_PLL:
-                       ret = external_clk[ddr3_clk];
+                       ret = external_clk[ddr3a_clk];
                        reg = KS2_DDR3APLLCTL0;
                        break;
                default:
index 0bd0fd6ac29e5b6e49de8913288a90c1decda388..00040591925a6142f083d9b9a4f38577554c00be 100644 (file)
@@ -47,7 +47,7 @@ static unsigned long pll_freq_get(int pll)
                        reg = KS2_ARMPLLCTL0;
                        break;
                case DDR3_PLL:
-                       ret = external_clk[ddr3_clk];
+                       ret = external_clk[ddr3a_clk];
                        reg = KS2_DDR3APLLCTL0;
                        break;
                default:
index 8fdc0f0e8358f3d755cfcbe02948aebdd1c63cab..e66ad692da9e91c437944194d2dca4f52a259f6f 100644 (file)
 #ifndef __ASM_ARCH_CLOCK_K2E_H
 #define __ASM_ARCH_CLOCK_K2E_H
 
-enum ext_clk_e {
-       sys_clk,
-       alt_core_clk,
-       pa_clk,
-       ddr3_clk,
-       mcm_clk,
-       pcie_clk,
-       sgmii_clk,
-       xgmii_clk,
-       usb_clk,
-       ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
        CLK(0, core_pll_clk)\
        CLK(1, pass_pll_clk)\
index 366bf0ee593bcdf06a4bf525605412658722d729..775a9cb418f0ee0c092c2ec085b05d255c37fb1c 100644 (file)
 #ifndef __ASM_ARCH_CLOCK_K2HK_H
 #define __ASM_ARCH_CLOCK_K2HK_H
 
-enum ext_clk_e {
-       sys_clk,
-       alt_core_clk,
-       pa_clk,
-       tetris_clk,
-       ddr3a_clk,
-       ddr3b_clk,
-       mcm_clk,
-       pcie_clk,
-       sgmii_srio_clk,
-       xgmii_clk,
-       usb_clk,
-       rp1_clk,
-       ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
        CLK(0, core_pll_clk)\
        CLK(1, pass_pll_clk)\
index e3f005a72cdd36ddf53b191b1c80b13ff05c2300..485746dea28af4cce88942d5d8e023d1f6121dbb 100644 (file)
 #ifndef __ASM_ARCH_CLOCK_K2L_H
 #define __ASM_ARCH_CLOCK_K2L_H
 
-enum ext_clk_e {
-       sys_clk,
-       alt_core_clk,
-       pa_clk,
-       tetris_clk,
-       ddr3_clk,
-       pcie_clk,
-       sgmii_clk,
-       usb_clk,
-       rp1_clk,
-       ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
        CLK(0, core_pll_clk)\
        CLK(1, pass_pll_clk)\
index de697c01eb8e076bb2490d6e8bb543620550b877..d0bcee72817f8e8819d1846171d999abb784f246 100644 (file)
@@ -55,6 +55,16 @@ enum {
        MAX_PLL_COUNT,
 };
 
+enum ext_clk_e {
+       sys_clk,
+       alt_core_clk,
+       pa_clk,
+       tetris_clk,
+       ddr3a_clk,
+       ddr3b_clk,
+       ext_clk_count /* number of external clocks */
+};
+
 enum clk_e {
        CLK_LIST(GENERATE_ENUM)
 };
@@ -72,6 +82,7 @@ struct pll_init_data {
        int pll_od;             /* PLL output divider */
 };
 
+extern unsigned int external_clk[ext_clk_count];
 extern const struct keystone_pll_regs keystone_pll_regs[];
 extern s16 divn_val[];
 extern int speeds[];
index e33cc64ea01f515fc48ea710d78980664c68e641..dc00cf62a5725a0d5e16b4e3d8b0b884d23bd0e5 100644 (file)
@@ -18,12 +18,7 @@ unsigned int external_clk[ext_clk_count] = {
        [sys_clk]       = 100000000,
        [alt_core_clk]  = 100000000,
        [pa_clk]        = 100000000,
-       [ddr3_clk]      = 100000000,
-       [mcm_clk]       = 312500000,
-       [pcie_clk]      = 100000000,
-       [sgmii_clk]     = 156250000,
-       [xgmii_clk]     = 156250000,
-       [usb_clk]       = 100000000,
+       [ddr3a_clk]     = 100000000,
 };
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
index b9e2b07b8ae6c15472f7d22929f99ecf4707c01c..6e681d7cb6fbdb86aed942508218af5e4552bd03 100644 (file)
@@ -21,12 +21,6 @@ unsigned int external_clk[ext_clk_count] = {
        [tetris_clk]    =       125000000,
        [ddr3a_clk]     =       100000000,
        [ddr3b_clk]     =       100000000,
-       [mcm_clk]       =       312500000,
-       [pcie_clk]      =       100000000,
-       [sgmii_srio_clk] =      156250000,
-       [xgmii_clk]     =       156250000,
-       [usb_clk]       =       100000000,
-       [rp1_clk]       =       123456789
 };
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
index 58a6cbd86eafcfe7f64dfca0500e8bf4df4d034f..70e25f10c423dcac1da15b21c67bc60fded54633 100644 (file)
@@ -19,10 +19,7 @@ unsigned int external_clk[ext_clk_count] = {
        [alt_core_clk]  = 100000000,
        [pa_clk]        = 122880000,
        [tetris_clk]    = 122880000,
-       [ddr3_clk]      = 100000000,
-       [pcie_clk]      = 100000000,
-       [sgmii_clk]     = 156250000,
-       [usb_clk]       = 100000000,
+       [ddr3a_clk]     = 100000000,
 };
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {