mmc: zynq_sdhci: Add common function to set input/output tapdelays

Remove setting tapdelays for different speeds separately. Instead use
the ITAP and OTAP delay values which are read from the device tree.
If the DT does not contain tap delay values, the predefined values
will be used for the same.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
index 13683701f64e5da85bb24c9c6f440364364a5ba0..1cab25f00a5ce3fce48a57f077fef4373e9e789d 100644 (file)
--- a/board/xilinx/zynqmp/tap_delays.c
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <zynqmp_tap_delay.h>
 #include <asm/arch/sys_proto.h>
 #include <linux/delay.h>
 #include <mmc.h>
@@ -26,34 +27,9 @@
 #define SD1_ITAPDLYENA_MASK            0x01000000
 #define SD1_ITAPDLYENA                 0x01000000
 #define SD0_ITAPDLYSEL_MASK            0x000000FF
-#define SD0_ITAPDLYSEL_HSD             0x00000015
-#define SD0_ITAPDLYSEL_SD_DDR50                0x0000003D
-#define SD0_ITAPDLYSEL_MMC_DDR50       0x00000012
-
 #define SD1_ITAPDLYSEL_MASK            0x00FF0000
-#define SD1_ITAPDLYSEL_HSD             0x00150000
-#define SD1_ITAPDLYSEL_SD_DDR50                0x003D0000
-#define SD1_ITAPDLYSEL_MMC_DDR50       0x00120000
-
 #define SD0_OTAPDLYSEL_MASK            0x0000003F
-#define SD0_OTAPDLYSEL_MMC_HSD         0x00000006
-#define SD0_OTAPDLYSEL_SD_HSD          0x00000005
-#define SD0_OTAPDLYSEL_SDR50           0x00000003
-#define SD0_OTAPDLYSEL_SDR104_B0       0x00000003
-#define SD0_OTAPDLYSEL_SDR104_B2       0x00000002
-#define SD0_OTAPDLYSEL_SD_DDR50                0x00000004
-#define SD0_OTAPDLYSEL_MMC_DDR50       0x00000006
-
 #define SD1_OTAPDLYSEL_MASK            0x003F0000
-#define SD1_OTAPDLYSEL_MMC_HSD         0x00060000
-#define SD1_OTAPDLYSEL_SD_HSD          0x00050000
-#define SD1_OTAPDLYSEL_SDR50           0x00030000
-#define SD1_OTAPDLYSEL_SDR104_B0       0x00030000
-#define SD1_OTAPDLYSEL_SDR104_B2       0x00020000
-#define SD1_OTAPDLYSEL_SD_DDR50                0x00040000
-#define SD1_OTAPDLYSEL_MMC_DDR50       0x00060000
-
-#define MMC_BANK2              0x2
 
 void zynqmp_dll_reset(u8 deviceid)
 {
@@ -74,149 +50,49 @@ void zynqmp_dll_reset(u8 deviceid)
                zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
 }
 
-static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
-{
-       if (deviceid == 0) {
-               /* Program OTAP */
-               if (bank == MMC_BANK2)
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
-                                         SD0_OTAPDLYSEL_SDR104_B2);
-               else
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
-                                         SD0_OTAPDLYSEL_SDR104_B0);
-       } else {
-               /* Program OTAP */
-               if (bank == MMC_BANK2)
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
-                                         SD1_OTAPDLYSEL_SDR104_B2);
-               else
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
-                                         SD1_OTAPDLYSEL_SDR104_B0);
-       }
-}
-
-static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
-{
-       if (deviceid == 0) {
-               /* Program ITAP */
-               zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
-                                 SD0_ITAPCHGWIN);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
-                                 SD0_ITAPDLYENA);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
-                                 SD0_ITAPDLYSEL_HSD);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
-               /* Program OTAP */
-               if (timing == MMC_TIMING_MMC_HS)
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
-                                         SD0_OTAPDLYSEL_MMC_HSD);
-               else
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
-                                         SD0_OTAPDLYSEL_SD_HSD);
-       } else {
-               /* Program ITAP */
-               zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
-                                 SD1_ITAPCHGWIN);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
-                                 SD1_ITAPDLYENA);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
-                                 SD1_ITAPDLYSEL_HSD);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
-               /* Program OTAP */
-               if (timing == MMC_TIMING_MMC_HS)
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
-                                         SD1_OTAPDLYSEL_MMC_HSD);
-               else
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
-                                         SD1_OTAPDLYSEL_SD_HSD);
-       }
-}
-
-static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
+void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay)
 {
        if (deviceid == 0) {
+               zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+                                 SD0_DLL_RST);
                /* Program ITAP */
-               zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
-                                 SD0_ITAPCHGWIN);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
-                                 SD0_ITAPDLYENA);
-               if (timing == MMC_TIMING_UHS_DDR50)
-                       zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
-                                         SD0_ITAPDLYSEL_SD_DDR50);
-               else
+               if (itap_delay) {
+                       zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+                                         SD0_ITAPCHGWIN);
+                       zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+                                         SD0_ITAPDLYENA);
                        zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
-                                         SD0_ITAPDLYSEL_MMC_DDR50);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
+                                         itap_delay);
+                       zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+                                         0x0);
+               }
+
                /* Program OTAP */
-               if (timing == MMC_TIMING_UHS_DDR50)
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
-                                         SD0_OTAPDLYSEL_SD_DDR50);
-               else
+               if (otap_delay)
                        zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
-                                         SD0_OTAPDLYSEL_MMC_DDR50);
-       } else {
-               /* Program ITAP */
-               zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
-                                 SD1_ITAPCHGWIN);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
-                                 SD1_ITAPDLYENA);
-               if (timing == MMC_TIMING_UHS_DDR50)
-                       zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
-                                         SD1_ITAPDLYSEL_SD_DDR50);
-               else
-                       zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
-                                         SD1_ITAPDLYSEL_MMC_DDR50);
-               zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
-               /* Program OTAP */
-               if (timing == MMC_TIMING_UHS_DDR50)
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
-                                         SD1_OTAPDLYSEL_SD_DDR50);
-               else
-                       zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
-                                         SD1_OTAPDLYSEL_MMC_DDR50);
-       }
-}
+                                         otap_delay);
 
-static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
-{
-       if (deviceid == 0) {
-               /* Program OTAP */
-               zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
-                                 SD0_OTAPDLYSEL_SDR50);
+               zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
        } else {
-               /* Program OTAP */
-               zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
-                                 SD1_OTAPDLYSEL_SDR50);
-       }
-}
-
-void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
-{
-       if (deviceid == 0)
-               zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
-                                 SD0_DLL_RST);
-       else
                zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
                                  SD1_DLL_RST);
+               /* Program ITAP */
+               if (itap_delay) {
+                       zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+                                         SD1_ITAPCHGWIN);
+                       zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+                                         SD1_ITAPDLYENA);
+                       zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+                                         (itap_delay << 16));
+                       zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+                                         0x0);
+               }
 
-       switch (timing) {
-       case MMC_TIMING_UHS_SDR25:
-               arasan_zynqmp_tap_hs(deviceid, timing, bank);
-               break;
-       case MMC_TIMING_UHS_SDR50:
-               arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
-               break;
-       case MMC_TIMING_UHS_SDR104:
-       case MMC_TIMING_MMC_HS200:
-               arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
-               break;
-       case MMC_TIMING_UHS_DDR50:
-               arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
-               break;
-       }
+               /* Program OTAP */
+               if (otap_delay)
+                       zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+                                         (otap_delay << 16));
 
-       if (deviceid == 0)
-               zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
-       else
                zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+       }
 }

diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h
index b07e3e069224212903f911bda2314782fd2188dc..7b713438f75249cfc2402fed650fe655ce7cd6a4 100644 (file)
--- a/include/zynqmp_tap_delay.h
+++ b/include/zynqmp_tap_delay.h
@@ -10,10 +10,11 @@
 
 #ifdef CONFIG_ARCH_ZYNQMP
 void zynqmp_dll_reset(u8 deviceid);
-void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank);
+void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay);
 #else
 inline void zynqmp_dll_reset(u8 deviceid) {}
-inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {}
+inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay,
+                                      u32 otap_delay) {}
 #endif
 
 #endif