arm: socfpga: soc64: Check FPGA Config status register before bridge reset

Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index a85c5aeef955235ebe583a372cdfa1b7610fa1f3..649d2f6ce245f5d5574fea612b7e86d149f26347 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -39,6 +39,11 @@ void socfpga_init_security_policies(void);
 void socfpga_sdram_remap_zero(void);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+       defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+int is_fpga_config_ready(void);
+#endif
+
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
 void socfpga_get_managers_addr(void);

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c90f63a754c0532ec3986011e7c51e866d1836b1..5e3f54a6a8c96a6a59c0832cb56bc3efbc2adfb9 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -88,8 +88,12 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
 #define SYSMGR_ECC_OCRAM_EN    BIT(0)
 #define SYSMGR_ECC_OCRAM_SERR  BIT(3)
 #define SYSMGR_ECC_OCRAM_DERR  BIT(4)
-#define SYSMGR_FPGAINTF_USEFPGA        0x1
+#define SYSMGR_FPGACONFIG_FPGA_COMPLETE                BIT(0)
+#define SYSMGR_FPGACONFIG_EARLY_USERMODE       BIT(1)
+#define SYSMGR_FPGACONFIG_READY_MASK   (SYSMGR_FPGACONFIG_FPGA_COMPLETE | \
+                                        SYSMGR_FPGACONFIG_EARLY_USERMODE)
 
+#define SYSMGR_FPGAINTF_USEFPGA        0x1
 #define SYSMGR_FPGAINTF_NAND   BIT(4)
 #define SYSMGR_FPGAINTF_SDMMC  BIT(8)
 #define SYSMGR_FPGAINTF_SPIM0  BIT(16)

diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 670bfa1a31fdd5d414b36de87564491fd52457f1..52868fb344818530f4bfb3a03e68a51548e1543b 100644 (file)
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -151,17 +151,19 @@ int arch_early_init_r(void)
        return 0;
 }
 
+/* Return 1 if FPGA is ready otherwise return 0 */
+int is_fpga_config_ready(void)
+{
+       return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
+               SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
+}
+
 void do_bridge_reset(int enable, unsigned int mask)
 {
        /* Check FPGA status before bridge enable */
-       if (enable) {
-               int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
-
-               if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
-                       ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
-               if (ret)
-                       return;
+       if (!is_fpga_config_ready()) {
+               puts("FPGA not ready. Bridge reset aborted!\n");
+               return;
        }
 
        socfpga_bridges_reset(enable);