The timer being used by this driver may have already been used by first
stage bootloader (e.g. ATF/preloader), and it's settings may differ from
what this driver is going to use.
This may cause issues, such as inaccurate timer frequency due to
incorrect clock divider.
This patch adds the initialization code to avoid them.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
if (!uc_priv->clock_rate)
return -EINVAL;
+ /*
+ * Initialize the timer:
+ * 1. set clock source to system clock with clock divider setting to 1
+ * 2. set timer mode to free running
+ * 3. reset timer counter to 0 then enable the timer
+ */
+ writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK);
+ writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE,
+ priv->base + MTK_GPT4_CTRL);
+
return 0;
}