x86: galileo: Add PCIe root port IRQ routing

Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index f119bf7f42c9e7d1f156dbb2f4e1790c195b1319..a4e16760d5e3f3c634e3e216f88b08397ec96713 100644 (file)
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -92,6 +92,18 @@
                                PCI_BDF(0, 21, 0) INTA PIRQE
                                PCI_BDF(0, 21, 1) INTB PIRQF
                                PCI_BDF(0, 21, 2) INTC PIRQG
+                               PCI_BDF(0, 23, 0) INTA PIRQA
+                               PCI_BDF(0, 23, 1) INTB PIRQB
+
+                               /* PCIe root ports downstream interrupts */
+                               PCI_BDF(1, 0, 0) INTA PIRQA
+                               PCI_BDF(1, 0, 0) INTB PIRQB
+                               PCI_BDF(1, 0, 0) INTC PIRQC
+                               PCI_BDF(1, 0, 0) INTD PIRQD
+                               PCI_BDF(2, 0, 0) INTA PIRQB
+                               PCI_BDF(2, 0, 0) INTB PIRQC
+                               PCI_BDF(2, 0, 0) INTC PIRQD
+                               PCI_BDF(2, 0, 0) INTD PIRQA
                        >;
                };
        };