arm: zynq: Add SLCR support with system reset

The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index 499ace4a62970bc108d592cbf29c57796988e651..388085dc2adde5ecadd6d8261ec4408a4de73b9e 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -30,6 +30,7 @@ LIB   = $(obj)lib$(SOC).o
 
 COBJS-y        := timer.o
 COBJS-y        += cpu.o
+COBJS-y        += slcr.o
 
 COBJS  := $(COBJS-y)
 

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index ab615cc7d4f8f2a92223daf322f8a64642451150..91618d3d8aea21e0b26365f1f7cb68f75032437b 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,11 +21,13 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/arch/sys_proto.h>
 
 inline void lowlevel_init(void) {}
 
 void reset_cpu(ulong addr)
 {
+       zynq_slcr_cpu_reset();
        while (1)
                ;
 }

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
new file mode 100644 (file)
index 0000000..788a8fd
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+
+#define SLCR_LOCK_MAGIC                0x767B
+#define SLCR_UNLOCK_MAGIC      0xDF0D
+
+static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
+
+void zynq_slcr_lock(void)
+{
+       if (!slcr_lock)
+               writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+}
+
+void zynq_slcr_unlock(void)
+{
+       if (slcr_lock)
+               writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+}
+
+/* Reset the entire system */
+void zynq_slcr_cpu_reset(void)
+{
+       /*
+        * Unlock the SLCR then reset the system.
+        * Note that this seems to require raw i/o
+        * functions or there's a lockup?
+        */
+       zynq_slcr_unlock();
+
+       /*
+        * Clear 0x0F000000 bits of reboot status register to workaround
+        * the FSBL not loading the bitstream after soft-reboot
+        * This is a temporary solution until we know more.
+        */
+       clrbits_le32(&slcr_base->reboot_status, 0xF000000);
+
+       writel(1, &slcr_base->pss_rst_ctrl);
+}

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
new file mode 100644 (file)
index 0000000..ad17b27
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define XPSS_SYS_CTRL_BASEADDR         0xF8000000
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+       u32 scl; /* 0x0 */
+       u32 slcr_lock; /* 0x4 */
+       u32 slcr_unlock; /* 0x8 */
+       u32 reserved1[125];
+       u32 pss_rst_ctrl; /* 0x200 */
+       u32 reserved2[21];
+       u32 reboot_status; /* 0x258 */
+};
+
+#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+
+#endif /* _ASM_ARCH_HARDWARE_H */

diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
new file mode 100644 (file)
index 0000000..e788900
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+extern void zynq_slcr_lock(void);
+extern void zynq_slcr_unlock(void);
+extern void zynq_slcr_cpu_reset(void);
+
+#endif /* _SYS_PROTO_H_ */