net: zynq_gem: Correct SGMII enable bit setting

Correct the SGMII enable bit position to 27 instead
of 31.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 0023b1689efe62b9bdf8b5e76822689af619bdb7..3319e10467d0a36c29e0d962428bf01a542c6684 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -57,7 +57,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_GEM_NWCFG_SPEED1000       0x00000400 /* 1Gbps operation */
 #define ZYNQ_GEM_NWCFG_FDEN            0x00000002 /* Full Duplex mode */
 #define ZYNQ_GEM_NWCFG_FSREM           0x00020000 /* FCS removal */
-#define ZYNQ_GEM_NWCFG_SGMII_ENBL      0x80000000 /* SGMII Enable */
+#define ZYNQ_GEM_NWCFG_SGMII_ENBL      0x08000000 /* SGMII Enable */
 #define ZYNQ_GEM_NWCFG_PCS_SEL         0x00000800 /* PCS select */
 #ifdef CONFIG_ARM64
 #define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x00100000 /* Div pclk by 64, max 160MHz */