armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions.  This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 4b425b8b6d297b8ca11e3ca277acbeed18087655..aa6a1849d4d351353d5ecd0a12e2aec45a3df491 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -234,6 +234,7 @@ int sata_init(void)
 #endif
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA);
        scsi_scan(0);
@@ -337,7 +338,9 @@ void fsl_lsch2_early_init_f(void)
 #endif
        /* Make SEC reads and writes snoopable */
        setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-                    SCFG_SNPCNFGCR_SECWRSNP);
+                    SCFG_SNPCNFGCR_SECWRSNP |
+                    SCFG_SNPCNFGCR_SATARDSNP |
+                    SCFG_SNPCNFGCR_SATAWRSNP);
 
        /*
         * Enable snoop requests and DVM message requests for

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index df5187195df32bb19f5bb72a1e56b904db76d37a..3d00909b2cf0894a7cc2f749fce60be5bd6e0edb 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -335,6 +335,8 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP                0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 0729b7f75dce2c0b221d59113142c4fa63a0fc6d..58e90d8d8819c24871aac575929320d3259a3b4a 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -61,6 +61,7 @@ struct cpu_type {
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
 #define AHCI_PORT_TRANS_CFG    0x08000029
+#define AHCI_PORT_AXICC_CFG    0x3fffffff
 
 /* AHCI (sata) register map */
 struct ccsr_ahci {