]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx9: soc: wait ssar when power on power domain
authorPeng Fan <peng.fan@nxp.com>
Thu, 19 Sep 2024 04:01:19 +0000 (12:01 +0800)
committerFabio Estevam <festevam@gmail.com>
Thu, 19 Sep 2024 03:12:41 +0000 (00:12 -0300)
SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.

Fixes: 0256577a83b ("imx: imx9: Add MIX power init")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/include/asm/arch-imx9/imx-regs.h
arch/arm/mach-imx/imx9/soc.c

index 76d241eab09adb63bdef7e5b426eaf8a9e3983eb..9953c33b73b670aa3fdc689ba724576749fe065f 100644 (file)
@@ -38,6 +38,7 @@
 #define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
 #define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
 #define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
 #define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
 
 #define IMG_CONTAINER_BASE             (0x80000000UL)
index f88e7a222dd46121fc051144b8085de37b523256..3ee2f3d881fce5fade05e38b387b5ca8211e3e36 100644 (file)
@@ -752,7 +752,7 @@ static int mix_power_init(enum mix_power_domain pd)
        /* power on */
        clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
        val = readl(&mix_regs->func_stat);
-       while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT)
+       while (val & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT)
                val = readl(&mix_regs->func_stat);
 
        return 0;