imx: imx8mp_evk: enable eth support

Add board code to configure the network interface
Add net defconfig

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 4f00b5a3a91f54f9dc9039182f68668849d0635e..0bf6ef58430554e7bdc2f72dec4a9e47543a1f7f 100644 (file)
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -139,3 +139,7 @@
 &wdog1 {
        u-boot,dm-spl;
 };
+
+&fec {
+       phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+};

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index f1c410ec78a545d7e90116c473599b946278ea5f..f5711155b70c8a7a35c716c886142a0d05c98a68 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -62,6 +62,8 @@
 #define DDRC_IPS_BASE_ADDR(X)  (0x3d400000 + ((X) * 0x2000000))
 #define DDR_CSD1_BASE_ADDR     0x40000000
 
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
+
 #if !defined(__ASSEMBLY__)
 #include <asm/types.h>
 #include <linux/bitops.h>

diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 034a349236e828cc8937b4962926929568ce7386..330b47fa5f92377ed8390006d317cdf554625a8c 100644 (file)
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -7,9 +7,13 @@
 #include <env.h>
 #include <errno.h>
 #include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <linux/delay.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm-generic/gpio.h>
 #include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/gpio.h>
 
@@ -40,10 +44,69 @@ int board_early_init_f(void)
        return 0;
 }
 
-int board_init(void)
+static void setup_fec(void)
+{
+       struct iomuxc_gpr_base_regs *gpr =
+               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+       /* Enable RGMII TX clk output */
+       setbits_le32(&gpr->gpr[1], BIT(22));
+}
+
+#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
+static iomux_v3_cfg_t const eqos_rst_pads[] = {
+       MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_eqos(void)
 {
+       imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
+                                        ARRAY_SIZE(eqos_rst_pads));
+
+       gpio_request(EQOS_RST_PAD, "eqos_rst");
+       gpio_direction_output(EQOS_RST_PAD, 0);
+       mdelay(15);
+       gpio_direction_output(EQOS_RST_PAD, 1);
+       mdelay(100);
+}
+
+static int setup_eqos(void)
+{
+       struct iomuxc_gpr_base_regs *gpr =
+               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+       setup_iomux_eqos();
+
+       /* set INTF as RGMII, enable RGMII TXC clock */
+       clrsetbits_le32(&gpr->gpr[1],
+                       IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+       setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+       return set_clk_eqos(ENET_125MHZ);
+}
+
+#if CONFIG_IS_ENABLED(NET)
+int board_phy_config(struct phy_device *phydev)
+{
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
        return 0;
 }
+#endif
+
+int board_init(void)
+{
+       int ret = 0;
+
+       if (CONFIG_IS_ENABLED(FEC_MXC)) {
+               setup_fec();
+
+               if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+                       ret = setup_eqos();
+       }
+
+       return ret;
+}
 
 int board_late_init(void)
 {

diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 6166d103e329813dfca8cc67e9f986574638d394..2e4f517c51591ea291b4f4ec4694b3cf48b1b006 100644 (file)
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -45,6 +45,9 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
@@ -74,8 +77,12 @@ CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_ESDHC_IMX=y
-CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y

diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 92091dfd6ba1e3cf6c2a0f54906616d90e764747..2f58ba3f9fcbba34565ca7a2c9b41346e0e554e2 100644 (file)
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -44,6 +44,22 @@
 
 #endif
 
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ETHPRIME                 "eth1" /* Set eqos to primary since we use its MDIO */
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          1
+#define FEC_QUIRK_ENET_MAC
+
+#define DWC_NET_PHYADDR                        1
+#ifdef CONFIG_DWC_ETH_QOS
+#define CONFIG_SYS_NONCACHED_MEMORY     (1 * SZ_1M)     /* 1M */
+#endif
+
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS              \
        "script=boot.scr\0" \