clk: rk3399: Fix eMMC get_clk reg offset

Actual eMMC get_clk register is clksel_con22 instead of
clksel_con21.

Fix it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 6a78837619eff53190a158ae87f0c6bce51a4bef..4caf3b5617653f708a1879ec2108d80e7ab84dfc 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -728,7 +728,7 @@ static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
                div = 2;
                break;
        case SCLK_EMMC:
-               con = readl(&cru->clksel_con[21]);
+               con = readl(&cru->clksel_con[22]);
                div = 1;
                break;
        default: