riscv: andes_plic: Fix some wrong configurations

Fix two wrong settings of andes plic driver as below:

1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
   int can help to fix wrong plic enabling setting in RV64.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 28568e4e2b6f7f0468d0b8fa5023b1af0d294a17..42394b9b6e1e272a643d55c8cf042b36d22311f3 100644 (file)
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -19,7 +19,7 @@
 #include <cpu.h>
 
 /* pending register */
-#define PENDING_REG(base, hart)        ((ulong)(base) + 0x1000 + (hart) * 8)
+#define PENDING_REG(base, hart)        ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
 /* enable register */
 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
 /* claim register */
@@ -46,7 +46,7 @@ static int init_plic(void);
 
 static int enable_ipi(int hart)
 {
-       int en;
+       unsigned int en;
 
        en = ENABLE_HART_IPI >> hart;
        writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
@@ -94,10 +94,13 @@ static int init_plic(void)
 
 int riscv_send_ipi(int hart)
 {
+       unsigned int ipi;
+
        PLIC_BASE_GET();
 
-       writel(SEND_IPI_TO_HART(hart),
-              (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
+       ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+       writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
+                               gd->arch.boot_hart));
 
        return 0;
 }