IPQ40xx: Add USB nodes

There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>

diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index 7b15df38d8b683ff6b637c407a7687fd25a1f99a..e0e4188e5db6fb312d743147aeb416213c581aa5 100644 (file)
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -90,5 +90,81 @@
                        gpio-bank-name="soc";
                        #gpio-cells = <2>;
                };
+
+               usb3_ss_phy: ssphy@9a000 {
+                       compatible = "qcom,usb-ss-ipq4019-phy";
+                       #phy-cells = <0>;
+                       reg = <0x9a000 0x800>;
+                       reg-names = "phy_base";
+                       resets = <&reset USB3_UNIPHY_PHY_ARES>;
+                       reset-names = "por_rst";
+                       status = "disabled";
+               };
+
+               usb3_hs_phy: hsphy@a6000 {
+                       compatible = "qcom,usb-hs-ipq4019-phy";
+                       #phy-cells = <0>;
+                       reg = <0xa6000 0x40>;
+                       reg-names = "phy_base";
+                       resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
+                       reset-names = "por_rst", "srif_rst";
+                       status = "disabled";
+               };
+
+               usb3: usb3@8af8800 {
+                       compatible = "qcom,dwc3";
+                       reg = <0x8af8800 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
+                                <&gcc GCC_USB3_SLEEP_CLK>,
+                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+                       clock-names = "master", "sleep", "mock_utmi";
+                       ranges;
+                       status = "disabled";
+
+                       dwc3@8a00000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x8a00000 0xf8000>;
+                               phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               dr_mode = "host";
+                               maximum-speed = "super-speed";
+                               snps,dis_u2_susphy_quirk;
+                       };
+               };
+
+               usb2_hs_phy: hsphy@a8000 {
+                       compatible = "qcom,usb-hs-ipq4019-phy";
+                       #phy-cells = <0>;
+                       reg = <0xa8000 0x40>;
+                       reg-names = "phy_base";
+                       resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
+                       reset-names = "por_rst", "srif_rst";
+                       status = "disabled";
+               };
+
+               usb2: usb2@60f8800 {
+                       compatible = "qcom,dwc3";
+                       reg = <0x60f8800 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
+                                <&gcc GCC_USB2_SLEEP_CLK>,
+                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+                       clock-names = "master", "sleep", "mock_utmi";
+                       ranges;
+                       status = "disabled";
+
+                       dwc3@6000000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x6000000 0xf8000>;
+                               phys = <&usb2_hs_phy>;
+                               phy-names = "usb2-phy";
+                               dr_mode = "host";
+                               maximum-speed = "high-speed";
+                               snps,dis_u2_susphy_quirk;
+                       };
+               };
        };
 };