arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar

The Jaguar SBC provides an M.2 slot connected to the pcie3 controller.
In contrast to a number of other boards the pcie-refclk is gpio-controlled,
so the necessary clock and is added to the list of pcie3 clocks.

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20240423074956.2622318-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 0ec7e1096332bc2b9bc881c21cfd234058f747b3 ]

(cherry picked from commit 76a89655ae740dddb57187b5b52071ed99187452)
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 7d7303f8ecbfb1dd30be3ee1498068c55e1a1c6a..678ed8b4dcc6e1d11b974e98fc96999f2ab0a546 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -72,6 +72,27 @@
                };
        };
 
+       /*
+        * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
+        * clock generator.
+        * The clock output is gated via the OE pin on the clock generator.
+        * This is modeled as a fixed-clock plus a gpio-gate-clock.
+        */
+       pcie_refclk_gen: pcie-refclk-gen-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+       };
+
+       pcie_refclk: pcie-refclk-clock {
+               compatible = "gpio-gate-clock";
+               clocks = <&pcie_refclk_gen>;
+               #clock-cells = <0>;
+               enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
+               pinctrl-names = "default";
+               pinctrl-0 = <&pcie30x4_clkreqn_m0>;
+       };
+
        pps {
                compatible = "pps-gpio";
                gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
@@ -353,6 +374,30 @@
        status = "okay";
 };
 
+&pcie30phy {
+       status = "okay";
+};
+
+&pcie3x4 {
+       /*
+        * The board has a gpio-controlled "pcie_refclk" generator,
+        * so add it to the list of clocks.
+        */
+       clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+                <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+                <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+                <&pcie_refclk>;
+       clock-names = "aclk_mst", "aclk_slv",
+                     "aclk_dbi", "pclk",
+                     "aux", "pipe",
+                     "ref";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>;
+       reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
+       vpcie3v3-supply = <&vcc3v3_mdot2>;
+       status = "okay";
+};
+
 &pinctrl {
        emmc {
                emmc_reset: emmc-reset {
@@ -371,6 +416,20 @@
                        rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
+
+       pcie30x4 {
+               pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
+                       rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               pcie30x4_perstn_m0: pcie30x4-perstn-m0 {
+                       rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               pcie30x4_waken_m0: pcie30x4-waken-m0 {
+                       rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>;
+               };
+       };
 };
 
 &saradc {