#define GPIO_OES 0x70 /* Output Enable Set */
#define GPIO_OEC 0x74 /* Output Enable Clear */
+#define NPCM8XX_NUM_GPIO_BANK 8
#define NPCM8XX_GPIO_PER_BANK 32
#define GPIOX_OFFSET 16
}
#endif
+static void npcm8xx_pinctrl_clear_events(struct npcm8xx_pinctrl_priv *priv)
+{
+ void __iomem *base;
+ int i;
+
+ for (i = 0; i < NPCM8XX_NUM_GPIO_BANK; i++) {
+ base = priv->gpio_base + (0x1000 * i);
+ clrbits_le32(base + GPIO_EVEN, 0xFFFFFFFF);
+ setbits_le32(base + GPIO_EVST, 0xFFFFFFFF);
+ }
+}
+
static struct pinctrl_ops npcm8xx_pinctrl_ops = {
.set_state = pinctrl_generic_set_state,
.get_pins_count = npcm8xx_get_pins_count,
if (IS_ERR(priv->rst_regmap))
return -EINVAL;
+ /*
+ * Clear all previous gpio events, otherwise it may produce
+ * unexpected interrupts during kernel booting.
+ */
+ npcm8xx_pinctrl_clear_events(priv);
return 0;
}