ARM: renesas: falcon: Enable RWDT reset for V3U Falcon

Enable RWDT reset on Reset Controller so that it can be used as
reset trigger source for V3U Falcon.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use one current_el() in board_init

diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index b7e7fd9003af0bca82535c1e80005cf2863be4f9..ab7464d0ee3623c69217f610b8c9a789b728b198 100644 (file)
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -83,21 +83,27 @@ int board_early_init_f(void)
        return 0;
 }
 
+#define RST_BASE       0xE6160000 /* Domain0 */
+#define RST_SRESCR0    (RST_BASE + 0x18)
+#define RST_SPRES      0x5AA58000
+#define RST_WDTRSTCR   (RST_BASE + 0x10)
+#define RST_RWDT       0xA55A8002
+
 int board_init(void)
 {
        /* address of boot parameters */
        gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
 
-       if (current_el() == 3)
+       if (current_el() == 3) {
                init_gic_v3();
 
+               /* Enable RWDT reset */
+               writel(RST_RWDT, RST_WDTRSTCR);
+       }
+
        return 0;
 }
 
-#define RST_BASE       0xE6160000 /* Domain0 */
-#define RST_SRESCR0    (RST_BASE + 0x18)
-#define RST_SPRES      0x5AA58000
-
 void reset_cpu(void)
 {
        writel(RST_SPRES, RST_SRESCR0);