arm: Move SYS_FSL_IFC_BANK_COUNT to Kconfig

Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index e8264f54fb951105c5bd2b54b253acbfdba8b97e..88983f4c181d1e6a6347e3e78fbe388eb4da3914 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -23,4 +23,9 @@ config MAX_CPUS
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_IFC_BANK_COUNT
+       int "Maximum banks of Integrated flash controller"
+       depends on ARCH_LS1021A
+       default 8
+
 endmenu

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 352d1d316ab88c35d7ce604c7bd6a326609fb204..c6cf7749ada48a8bf2fe484ff17c65dfaeb5679b 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -50,4 +50,11 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
+config SYS_FSL_IFC_BANK_COUNT
+       int "Maximum banks of Integrated flash controller"
+       depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+       default 4 if ARCH_LS1043A
+       default 4 if ARCH_LS1046A
+       default 8 if ARCH_LS2080A
+
 endmenu

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 572fa9469383dc8a0f5f67f8842d2d0ae7956016..2f10ab7f0e69e5eb2d16bd323bb8a635383f89d3 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -30,7 +30,6 @@
 #define CONFIG_SYS_MEM_RESERVE_SECURE  (2048 * 1024)   /* 2MB */
 
 #ifdef CONFIG_LS2080A
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             3
 #define CONFIG_SYS_FSL_HAS_DP_DDR              /* Runtime check to confirm */
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
@@ -174,7 +173,6 @@
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
 #define CONFIG_SYS_NUM_FM1_10GEC               1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT          4
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
@@ -213,7 +211,6 @@
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8
 #define CONFIG_SYS_NUM_FM1_10GEC               2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT          4
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE